Amplitude noise suppression using a high gain phase sensitive amplifier as a limiting amplifier

1996 ◽  
Vol 32 (7) ◽  
pp. 677 ◽  
Author(s):  
A. Takada ◽  
W. Imajuku
2006 ◽  
Vol 14 (1) ◽  
pp. 348 ◽  
Author(s):  
Yoshiyasu Ueno ◽  
Masashi Toyoda ◽  
Rei Suzuki ◽  
Youhe Nagasue

2015 ◽  
Vol 54 (13) ◽  
pp. D38 ◽  
Author(s):  
Mikael Lassen ◽  
Anders Brusch ◽  
David Balslev-Harder ◽  
Jan C. Petersen

2012 ◽  
Vol 30 (5) ◽  
pp. 764-771 ◽  
Author(s):  
Alexandros Fragkos ◽  
Adonis Bogris ◽  
Dimitris Syvridis ◽  
Richard Phelan

2003 ◽  
Vol 13 (01) ◽  
pp. 239-263
Author(s):  
T. MASUDA ◽  
N. SHIRAMIZU ◽  
E. OHUE ◽  
K. ODA ◽  
R. HAYAMI ◽  
...  

Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifier, a common-base input stage is introduced. In order to have high gain and wide bandwidth simultaneously, active load circuits composed of a differential transimpedance amplifier are used for the AGC amplifier, the limiting amplifier, and the decision circuit. Full-rate clocking is employed to reduce the influence caused by clock-duty variation in digital circuits such as the decision circuit, the demultiplexer, and the multiplexer. All ICs were characterized by using on-wafer probes, and some of them were built in brass-packages for bit-error rate measurement.


1998 ◽  
Vol 09 (02) ◽  
pp. 437-472 ◽  
Author(s):  
Z. LAO ◽  
M. LANG ◽  
V. HURM ◽  
Z. WANG ◽  
A. THIEDE ◽  
...  

Using our 0.2 and 0.3 μm AlGaAs/GaAs/AlGaAs quantum well HEMT technology, we have developed a chip set for 20–40 Gbit/s fiber-optical digital transmission systems. In this paper we describe nine analog and digital receiver ICs: a 22 GHz high-gain transimpedance amplifier, a 20 Gbit/s OEIC front-end optical receiver, a 25 Gbit/s automatic-gain-control amplifier, a limiting amplifier with a differential gain of 26 dB and a bandwidth of 27.7 GHz, a 20–40 Gbit/s clock recovery, a 20 Gbit/s low-power Master-Slave-D-Flipflop with 24 mW power dissipation, a parallel data decision and a 1:4 demultiplexer, both for bit rates of 40 Gbit/s, and a 30 GHz static frequency divider, respectively. All chips were characterized on wafers with 50 Ω coplanar test probes.


2017 ◽  
Vol 27 (01) ◽  
pp. 1850007 ◽  
Author(s):  
Yutong Ying ◽  
Xuefei Bai ◽  
Fujiang Lin

This paper presents a low-power, high gain-bandwidth product (GBW) gain cell for gigabits-per-second communications. Based on this gain cell, a large GBW limiting amplifier (LA) and two types of high oscillation-frequency ring oscillators (ROs) are implemented with good energy efficiencies. Fabricated in the 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed LA can support 1.25[Formula: see text]Gbps data-rate with a measured GBW of 338[Formula: see text]GHz under 5[Formula: see text]mW. The proposed single- and multi-loop ROs obtain a simulated typical oscillation frequency of 5.26[Formula: see text]GHz and 6.96[Formula: see text]GHz, respectively, under 6.2 mW, which is less than one-eighth the power consumption of published ROs at similar frequencies in the same process.


2016 ◽  
Vol 63 (4) ◽  
pp. 356-360 ◽  
Author(s):  
Inyong Kwon ◽  
Taehoon Kang ◽  
Byron T. Wells ◽  
Lawrence D'Aries ◽  
Mark D. Hammig

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