High speed GaAs digital integrated circuit with clock frequency of 4.1 GHz

1981 ◽  
Vol 17 (8) ◽  
pp. 291 ◽  
Author(s):  
R. Yamamoto ◽  
A. Higashisaka
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Clock Frequency ◽  
Digital Integrated Circuit

GaAs HBT's for high-speed digital integrated circuit applications

1993 ◽  
Vol 81 (12) ◽  
pp. 1727-1743 ◽  
Author(s):  
C.T.M. Chang ◽  
Han-Tzong Yuan
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Digital Integrated Circuit

Optical Data Transmission Between High Speed Digital Integrated Circuit Chips

1986 ◽  
Author(s):  
M. K. Kilcoyne ◽  
D. Kasemset ◽  
R. Asatourian ◽  
S. Beccue ◽  
John A. Neff
Keyword(s):  
Integrated Circuit ◽  
Data Transmission ◽  
High Speed ◽  
Optical Data ◽  
Digital Integrated Circuit

scholarly journals Multilayer Structure of a New Portable, Low-Cost and Reversible Arithmetic and Logic Unit using High-Speed and Low-Power “QCA” Technology with Good-Scalability.

2019 ◽  
Vol 8 (4) ◽  
pp. 10568-10575
Keyword(s):  
Cellular Automata ◽  
Low Power ◽  
Integrated Circuit ◽  
Multilayer Structure ◽  
High Speed ◽  
Low Cost ◽  
Cmos Technology ◽  
Reversible Logic ◽  
Clock Frequency ◽  
Logic Unit

All nano-technologies including “QCA” (Quantumdot Cellular Automata) is widely used in today‟s world to reduce the power dissipation, area and delay. “QCA” is a magnify technology with huge advantages such as: high-speed, highdensity, faster-switching and higher clock-frequency which is rapidly used for Integrated-Circuit (“IC”) design. Quantum-dot Cellular Automata is an useful and appropriate alternative of the “CMOS-technology” because of its various advantages such as: it‟s high-frequency, less power leakage and less required area. An “ALU” (arithmetic and logic unit) is applying for all types of arithmetic-logical performances and it widely used in digital circuits for all types of arithmetic and logical operations. The reversible-Logic an authentic solution in low-power and low-cost technology. This paper presents a latest 3-D or multilayer structure of ALU using reversible-computing and also non-reversible logic which gives a comparative outcome with low supply-power and delay. The complexity of the formation and the engrossed size of this model is low. „AND-Gate‟, „OR-Gate‟ ,„XOR-Gate‟ and the reversible „TSG-Gate‟ and also the non-reversible model of “FullAdder” are used to design the suggested model of this paper through the “QCA Designer” software (for simulation).This design reduce the size of the model up to 0.11 µm2 with three layers which is also compared to the formation in the “Xilinx” software.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

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