Finite-length binary phase codes for digital pulse compression

1976 ◽  
Vol 12 (8) ◽  
pp. 197 ◽  
Author(s):  
M.W. Jelffs
2020 ◽  
Vol 57 (19) ◽  
pp. 193201
Author(s):  
李百宏 Li Baihong ◽  
夏志广 Xia Zhiguang ◽  
赵鹏达 Zhao Pengda ◽  
项晓 Xiang Xiao ◽  
董瑞芳 Dong Ruifang ◽  
...  

2014 ◽  
Vol 1049-1050 ◽  
pp. 1718-1721
Author(s):  
Yan Xin Yu ◽  
Chun Yang Wang ◽  
Yu Chen ◽  
Ke Yang

Pulse compression technology is one of the key technologies in the field of modern radar signal processing, can effectively solve the contradiction between action distance and resolution. In this paper, a radar digital pulse compression system is designed and implemented based on FPGA with linear frequency modulated signal. The digital pulse compression module is designed using FFT IP core which can be reused in different periods of DPC, respectively performing FFT and IFFT calculation, so that the hardware consumption is saved significantly. Therefore, compared with other systems, the system designed in this paper has the characters of fast processing speed, high degree of modularity, real-time processing and short development cycle.


2013 ◽  
Vol 734-737 ◽  
pp. 3244-3247
Author(s):  
Ben Cheng Yu ◽  
Zhi Hao Yin ◽  
Yong Yang ◽  
Zhi Feng Wang

Linear frequency modulated signal and the two-phase encoded signals are widely used in pulse compression radar system derived, based on the analysis of the two signals, a linear frequency modulated with chaotic two-phase coding complex modulated signals. Versatility advantages of simple structure, radar signal processing using DSP signal processing devices. TI's TMS320C6713 DSP as the core basis works to achieve a common structure, the composite modulation signal frequency domain digital pulse compression processing, given the realization of the system block diagram and pulse pressure results. The results showed that the composite modulation signal is easy to produce and handle, and works to achieve feasible.


2012 ◽  
Vol 236-237 ◽  
pp. 923-928
Author(s):  
Xiu Qing Zhang ◽  
Guo Chen An ◽  
Xiao Jun Wang

In this paper, a design method of high-speed, real-time digital pulse compression module based on Xilinx FPGA devices and Monbit receiver is introduced. A novel changeable-points of 256 or 1024 for three channels Digital Pulse Compression(DPC) with realizing FFT , complex-multiplication and IFFT function are presented which is accomplished by FPGA. A top-down flow has been used in the system. The whole design, which characters high stability, small logic resource occupation, low power consumption, is implemented with only one chip of FPGA XC2V500-5 for one channel. It takes 73.31us to complete a 1024-point DPC. Compared with the MATLAB simulation results, our module can accomplish function of 32k points digital pulse compression of 200MSPS throughput.


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