Near‐zero dead zone phase frequency detector with wide input frequency difference

2015 ◽  
Vol 51 (14) ◽  
pp. 1059-1061 ◽  
Author(s):  
J. Strzelecki ◽  
S. Ren
Keyword(s):  
Dead Zone ◽  
Frequency Difference ◽  
Input Frequency ◽  
Phase Frequency Detector ◽  
Frequency Detector

scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

A Novel Design of high performance low power phase frequency Detector for CMOS PLL frequency Synthesizer

2019 ◽  
Vol 09 ◽  
Author(s):  
Monika Bhardwaj ◽  
Sujata Pandey ◽  
Neeta Pandey
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Operating Frequency ◽  
Feedback Signal ◽  
Input Frequency ◽  
Phase Frequency Detector ◽  
Pll Frequency Synthesizer ◽  
Frequency Detector

Aims: A high performance low power phase frequency detector is designed and simulated. The various different parameters of the circuit are obtained through various type of simulations. We worked mainly upon the power dissipation, power supply, input frequency range and its area. The proposed PFD will have the locking capability i.e. to lock at the edges either on the rising or falling edge w.r.t the reference and the feedback signal. The proposed design will have the very high performance and ultra-low phase noise. It has the added advantage of low cost and the compact size. Objective: The primary objective is to design a low power phase frequency detector for CMOS PLL Frequency Synthesizer using lows power technique. Method: The pass transistor logic is used in the circuit to eliminate the reset path. By this change of the path the operating frequency and operating speed both are increased in the proposed design. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD design will have a less number of transistors and also a low consumption of power. The output pulses of the PFD at phase difference of 0, 0,п/2, п, 3п/2, 2п will have its average voltage as 0, VDD and VDD/2. The proposed phase detector will perfectly detect the phase difference between two signals so that the harmonics problem can be minimized. Result: The proposed design is having its operating frequency as 5GHz over the conventional one which has its frequency as 800MHz. Power dissipation in the proposed design is reduced due to less number of transistors used as compared with the conventional one. The operating region has become much wider for proposed design as it is having operating frequency much higher than that of the conventional one. Conclusion: The proposed PFD will increase the locking capability on the both rise and fall edge w.r.t. the reference and the feedback signal. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD circuit will have a less number of transistors and also a low consumption of power 7.14 mW.

scholarly journals A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1502
Author(s):  
Waseem Abbas ◽  
Zubair Mehmood ◽  
Munkyo Seo
Keyword(s):  
Frequency Synthesizer ◽  
Dead Zone ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Chip Area ◽  
V Band ◽  
Locking Range ◽  
Frequency Detector

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

2020 ◽  
Vol 13 (4) ◽  
pp. 516-530
Author(s):  
Suraj K. Saw ◽  
Madhusudan Maiti ◽  
Preetisudha Meher ◽  
Alak Majumder
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Dead Zone ◽  
Cmos Technology ◽  
Switching Noise ◽  
Phase Frequency Detector ◽  
Layout Area ◽  
Frequency Detector ◽  
Lock In

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors. Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V. Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

scholarly journals High‐speed, low power, and dead zone improved phase frequency detector

2019 ◽  
Vol 13 (7) ◽  
pp. 1056-1062 ◽  
Author(s):  
Amir Fathi ◽  
Morteza Mousazadeh ◽  
Abdollah Khoei
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dead Zone ◽  
Phase Frequency Detector ◽  
Frequency Detector
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