Exploration of
            k
            c
            ‐cycle transient fault‐secured datapath and loop unrolling factor for control data flow graphs during high‐level synthesis

A. Sengupta

doi:10.1049/el.2014.4393

Exploration of k c ‐cycle transient fault‐secured datapath and loop unrolling factor for control data flow graphs during high‐level synthesis

Electronics Letters ◽

10.1049/el.2014.4393 ◽

2015 ◽

Vol 51 (7) ◽

pp. 562-564 ◽

Cited By ~ 8

Author(s):

A. Sengupta

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Control Data ◽

Transient Fault ◽

Loop Unrolling ◽

C Cycle ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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Low cost fault tolerance against k c -cycle and k m -unit transient for loop based control data flow graphs during physically aware high level synthesis

Microelectronics Reliability ◽

10.1016/j.microrel.2017.05.023 ◽

2017 ◽

Vol 74 ◽

pp. 88-99 ◽

Cited By ~ 6

Author(s):

Anirban Sengupta ◽

Deepak Kachave

Keyword(s):

Fault Tolerance ◽

Data Flow ◽

Low Cost ◽

High Level Synthesis ◽

Control Data ◽

C Cycle ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High level synthesis through folding of data flow graphs: Optimal intra-node scheduling

Microprocessing and Microprogramming ◽

10.1016/0165-6074(93)90063-q ◽

1993 ◽

Vol 39 (2-5) ◽

pp. 89-92 ◽

Cited By ~ 2

Author(s):

Anna Antola ◽

Fausto Distante ◽

Andrea Marchese

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Node Scheduling ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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A high-level synthesis system for digital signal processing based on enumerating data-flow graphs

Proceedings of 1998 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1998.669463 ◽

2002 ◽

Author(s):

N. Togawa ◽

T. Hisaki ◽

M. Yanagisawa ◽

T. Ohtsuki

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Data Flow ◽

Digital Signal ◽

High Level Synthesis ◽

Synthesis System ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High Level Synthesis of Asynchronous Circuits from Data Flow Graphs

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-24154-3_32 ◽

2011 ◽

pp. 317-330

Author(s):

Rene van Leuken ◽

Tom van Leeuwen ◽

Huib Lincklaen Arriens

Keyword(s):

Data Flow ◽

Asynchronous Circuits ◽

High Level Synthesis ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High level synthesis of multi-precision data flow graphs

VLSI Design 2001. Fourteenth International Conference on VLSI Design ◽

10.1109/icvd.2001.902693 ◽

2002 ◽

Cited By ~ 7

Author(s):

V. Agrawal ◽

A. Pande ◽

M.M. Mehendale

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Precision Data ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High level synthesis of data flow graphs using integer linear programming for switching power reduction

2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies ◽

10.1109/icsccn.2011.6024597 ◽

2011 ◽

Cited By ~ 1

Author(s):

S. Anbu Yazhini ◽

D.S. Harish Ram

Keyword(s):

Linear Programming ◽

Integer Linear Programming ◽

Data Flow ◽

Power Reduction ◽

High Level Synthesis ◽

Switching Power ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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Intellectual property core protection of control data flow graphs using robust watermarking during behavioural synthesis based on user resource constraint and loop unrolling factor

Electronics Letters ◽

10.1049/el.2015.3879 ◽

2016 ◽

Vol 52 (6) ◽

pp. 439-441 ◽

Cited By ~ 4

Author(s):

A. Sengupta ◽

S. Bhadauria

Keyword(s):

Intellectual Property ◽

Data Flow ◽

Resource Constraint ◽

Robust Watermarking ◽

Control Data ◽

Loop Unrolling ◽

Data Flow Graphs ◽

Flow Graphs

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Accelerated SAT-based scheduling of control/data flow graphs

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106801 ◽

2003 ◽

Cited By ~ 7

Author(s):

S.O. Memik ◽

F. Fallah

Keyword(s):

Data Flow ◽

Control Data ◽

Data Flow Graphs ◽

Flow Graphs

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Global resource sharing for synthesis of control data flow graphs on FPGAs

10.1109/dac.2003.1219090 ◽

2004 ◽

Cited By ~ 5

Author(s):

S.O. Memik ◽

G. Memik ◽

R. Jafari ◽

E. Kursun

Keyword(s):

Resource Sharing ◽

Data Flow ◽

Control Data ◽

Data Flow Graphs ◽

Flow Graphs

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High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs

Microprocessing and Microprogramming ◽

10.1016/0165-6074(94)90020-5 ◽

1994 ◽

Vol 40 (10-12) ◽

pp. 693-696

Author(s):

Anna Antola ◽

Fausto Distante ◽

Andrea Marches

Keyword(s):

Data Flow ◽

Architectural Synthesis ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs ◽

Cycle Detection

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