Real-time application to multiprocessor-system-on-chip mapping strategy for system-level design tool

2009 ◽  
Vol 45 (12) ◽  
pp. 613 ◽  
Author(s):  
Z.J. Jia ◽  
T. Bautista ◽  
A. Núñez
Keyword(s):  
Real Time ◽  
System On Chip ◽  
Design Tool ◽  
System Level ◽  
Multiprocessor System ◽  
System Level Design ◽  
Mapping Strategy ◽  
Level Design ◽  
On Chip ◽  
Real Time Application

Systemc and OCAPI-XL Based System-Level Design for Reconfigurable Systems-on-Chip

2006 ◽  
pp. 255-269 ◽  
Author(s):  
Kari Tiensyrjä ◽  
Miroslav Cupak ◽  
Kostas Masselos ◽  
Marko Pettissalo ◽  
Konstantinos Potamianos ◽  
...  
Keyword(s):  
System Level ◽  
Reconfigurable Systems ◽  
System Level Design ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

2014 ◽  
pp. 150-179
Author(s):  
Haoyuan Ying ◽  
Klaus Hofmann ◽  
Thomas Hollstein
Keyword(s):  
Embedded Systems ◽  
Design Optimization ◽  
Optimization Methods ◽  
Design Methods ◽  
System Level ◽  
System Level Design ◽  
Level Design ◽  
On Chip ◽  
Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

A system-level design methodology for application-specific networks-on-chip

2009 ◽  
Vol 3 (3) ◽  
pp. 167-177 ◽  
Author(s):  
Alexandros Bartzas ◽  
Lazaros Papadopoulos ◽  
Dimitrios Soudris
Keyword(s):  
Design Methodology ◽  
System Level ◽  
System Level Design ◽  
Networks On Chip ◽  
Level Design ◽  
On Chip ◽  
Application Specific
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