A GmC filter design methodology for high-speed continuous time-delta A/D converters in 90 nm standard CMOS

2005 ◽  
Author(s):  
R. Schoofs
Keyword(s):  
Continuous Time ◽  
High Speed ◽  
Design Methodology ◽  
Filter Design

scholarly journals Robust H∞ Loop Shaping Controller Synthesis for SISO Systems by Complex Modular Functions

2021 ◽  
Vol 26 (1) ◽  
pp. 21
Author(s):  
Ahmad Taher Azar ◽  
Fernando E. Serrano ◽  
Nashwa Ahmad Kamal
Keyword(s):  
Design Methodology ◽  
Closed Loop ◽  
Complex Analysis ◽  
Controller Design ◽  
Filter Design ◽  
Design Procedure ◽  
Elliptic Functions ◽  
Loop System ◽  
Closed Loop System ◽  
Loop Shaping

In this paper, a loop shaping controller design methodology for single input and a single output (SISO) system is proposed. The theoretical background for this approach is based on complex elliptic functions which allow a flexible design of a SISO controller considering that elliptic functions have a double periodicity. The gain and phase margins of the closed-loop system can be selected appropriately with this new loop shaping design procedure. The loop shaping design methodology consists of implementing suitable filters to obtain a desired frequency response of the closed-loop system by selecting appropriate poles and zeros by the Abel theorem that are fundamental in the theory of the elliptic functions. The elliptic function properties are implemented to facilitate the loop shaping controller design along with their fundamental background and contributions from the complex analysis that are very useful in the automatic control field. Finally, apart from the filter design, a PID controller loop shaping synthesis is proposed implementing a similar design procedure as the first part of this study.

Comparison of the reluctance laminated and solid rotor synchronous machine operating at high temperatures

2019 ◽  
Vol 38 (4) ◽  
pp. 1111-1119 ◽  
Author(s):  
Marcin Lefik ◽  
Krzysztof Komeza ◽  
Ewa Napieralska-Juszczak ◽  
Daniel Roger ◽  
Piotr Andrzej Napieralski
Keyword(s):  
High Speed ◽  
Design Methodology ◽  
Three Dimensional ◽  
Synchronous Machine ◽  
Point Of View ◽  
Heat Sources ◽  
Model Calculations ◽  
Content Type ◽  
Thermal Phenomenon ◽  
Practical Implications

Purpose The purpose of this paper is to present a comparison between reluctance synchronous machine-enabling work at high internal temperature (HT° machine) with laminated and solid rotor. Design/methodology/approach To obtain heat sources for the thermal model, calculations of the electromagnetic field were made using the Opera 3D program including effect of rotation and the resulting eddy current losses. To analyse the thermal phenomenon, the 3D coupled thermal-fluid (CFD) model is used. Findings The presented results show clearly that laminated construction is much better from a point of view of efficiency and temperature. However, solid construction can be interesting for high speed machines due to their mechanical robustness. Research limitations/implications The main problem, despite the use of parallel calculations, is the long calculation time. Practical implications The obtained simulation and experimental results show the possibility of building a machine operating at a much higher ambient temperature than it was previously produced for example in the vicinity of the aircraft turbines. Originality/value The paper presents the application of fully three-dimensional coupled electromagnetic and thermal analysis of new machine constructions designed for elevated temperature.

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

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