Bandpass delta-sigma modulators for direct IF and RF sampling digital receivers implemented in InP HBT IC technology

1999 ◽  
Author(s):  
J.F. Jensen
Keyword(s):  
Delta Sigma ◽  
Digital Receivers ◽  
Ic Technology ◽  
Rf Sampling

1-bit Feedforward Distortion Compensation Technology for Bandpass Delta-Sigma Modulation

2016 ◽  
Vol E99.B (5) ◽  
pp. 1087-1092 ◽  
Author(s):  
Takashi MAEHATA ◽  
Suguru KAMEDA ◽  
Noriharu SUEMATSU
Keyword(s):  
Distortion Compensation ◽  
Delta Sigma ◽  
Delta Sigma Modulation

A Delta-Sigma Modulator Using a Non-uniform Quantizer Adjusted for the Probability Density of Input Signals

2012 ◽  
Vol E95.B (7) ◽  
pp. 2257-2265
Author(s):  
Toru KITAYABU ◽  
Mao HAGIWARA ◽  
Hiroyasu ISHIKAWA ◽  
Hiroshi SHIRAI
Keyword(s):  
Probability Density ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Input Signals

Cancellation for Asymmetrical Waveform in 1-bit Bandpass Delta-Sigma Modulators

2017 ◽  
Vol E100.B (6) ◽  
pp. 1017-1022 ◽  
Author(s):  
Takashi MAEHATA ◽  
Suguru KAMEDA ◽  
Noriharu SUEMATSU
Keyword(s):  
Delta Sigma

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

2011 ◽  
Vol E94-C (6) ◽  
pp. 1065-1068 ◽  
Author(s):  
Zule XU ◽  
Jun Gyu LEE ◽  
Shoichi MASUI
Keyword(s):  
Delta Sigma

Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps

2004 ◽  
Author(s):  
T. Zanon ◽  
W. Maly
Keyword(s):  
Geometric Characterization ◽  
Deformation Characteristics ◽  
Analysis Study ◽  
Preliminary Results ◽  
Failure Patterns ◽  
Yield Learning ◽  
Sram Memory ◽  
Viable Approach ◽  
Ic Technology

Abstract Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

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