Techniques for improving the error resilience of MPEG-5 codecs

1996 ◽  
Author(s):  
R.E.M. Swann
Keyword(s):  
Error Resilience

Security Threat Analyses and Attack Models for Approximate Computing Systems

2021 ◽  
Vol 26 (4) ◽  
pp. 1-31
Author(s):  
Pruthvy Yellu ◽  
Landon Buell ◽  
Miguel Mark ◽  
Michel A. Kinsy ◽  
Dongpeng Xu ◽  
...  
Keyword(s):  
Error Resilience ◽  
Security Threats ◽  
Approximate Computing ◽  
Security Threat ◽  
Security Vulnerabilities ◽  
Computing Systems ◽  
Quantitative Analyses ◽  
Resilience Mechanisms ◽  
The Impact ◽  
Attack Models

Approximate computing (AC) represents a paradigm shift from conventional precise processing to inexact computation but still satisfying the system requirement on accuracy. The rapid progress on the development of diverse AC techniques allows us to apply approximate computing to many computation-intensive applications. However, the utilization of AC techniques could bring in new unique security threats to computing systems. This work does a survey on existing circuit-, architecture-, and compiler-level approximate mechanisms/algorithms, with special emphasis on potential security vulnerabilities. Qualitative and quantitative analyses are performed to assess the impact of the new security threats on AC systems. Moreover, this work proposes four unique visionary attack models, which systematically cover the attacks that build covert channels, compensate approximation errors, terminate normal error resilience mechanisms, and propagate additional errors. To thwart those attacks, this work further offers the guideline of countermeasure designs. Several case studies are provided to illustrate the implementation of the suggested countermeasures.

Concealment Support and Error Resilience for HEVC to Improve Consumer Quality of Experience

2021 ◽  
pp. 1-1
Author(s):  
Gosala Kulupana ◽  
Dumidu S. Talagala ◽  
Hemantha Kodikara Arachchi ◽  
Mobolaji Akinola ◽  
Anil Fernando
Keyword(s):  
Quality Of Experience ◽  
Error Resilience

scholarly journals A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

2019 ◽  
Vol 9 (22) ◽  
pp. 4733
Author(s):  
Cuiping Shao ◽  
Huiyun Li ◽  
Zheng Wang ◽  
Jiayan Fang
Keyword(s):  
Image Processing ◽  
Principal Component Analysis ◽  
Principal Component ◽  
Error Resilience ◽  
Component Analysis ◽  
Cmos Technology ◽  
Error Correcting Codes ◽  
Memory Storage ◽  
Protection Scheme ◽  
Bit Flip

Nanoscale CMOS technology has encountered severe reliability issues especially in on-chip memory. Conventional word-level error resilience techniques such as Error Correcting Codes (ECC) suffer from high physical overhead and inability to correct increasingly reported multiple bit flip errors. On the other hands, state-of-the-art applications such as image processing and machine learning loosen the requirement on the levels of data protection, which result in dedicated techniques of approximated fault tolerance. In this work, we introduce a novel error protection scheme for memory, based on feature extraction through Principal Component Analysis and the modular-wise technique to segment the data before PCA. The extracted features can be protected by replacing the fault vector with the averaged confinement vectors. This approach confines the errors with either single or multi-bit flips for generic data blocks, whilst achieving significant savings on execution time and memory usage compared to traditional ECC techniques. Experimental results of image processing demonstrate that the proposed technique results in a reconstructed image with PSNR over 30 dB, while robust against both single bit and multiple bit flip errors, with reduced memory storage to just 22.4% compared to the conventional ECC-based technique.

A Systematic Methodology for Evaluating the Error Resilience of GPGPU Applications

2016 ◽  
Vol 27 (12) ◽  
pp. 3397-3411 ◽  
Author(s):  
Bo Fang ◽  
Karthik Pattabiraman ◽  
Matei Ripeanu ◽  
Sudhanva Gurumurthi
Keyword(s):  
Error Resilience ◽  
Systematic Methodology
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