A single chip for optimal edge detection

1995 ◽  
Author(s):  
N. Zarka
Keyword(s):  
Edge Detection ◽  
Single Chip

Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visual Communication

1997 ◽  
Vol 07 (05) ◽  
pp. 441-457
Author(s):  
Koji Miyanohana ◽  
Gen Fujita ◽  
Kazuhiro Yanagida ◽  
Takao Onoye ◽  
Isao Shirakawa
Keyword(s):  
Edge Detection ◽  
Visual Communication ◽  
Cmos Technology ◽  
Main Theme ◽  
Bit Rate ◽  
Single Chip ◽  
Low Bit Rate ◽  
Vector Quantizer ◽  
Block Level ◽  
Element Array

A single chip encoder-decoder dedicated to low bit rate visual communication is proposed, with the main theme focused on the object extraction and vector quantization. New schemes are introduced into an edge detector so as to extract objects by means of the block-level edge detection in conjunction with the pel-level edge detection and into a PE (Processing Element) array so as to be shared by the vector quantizer and the motion estimator. Owing to sophisticated architectures, these CODEC facilities have been implemented in 72.24 mm2 by a 0.6 μm triple-metal CMOS technology, which can enable the visual communication of QCIF (176 × 144) 10 fps pictures at a bit rate of 32 Kbps or less. The designed encoder-decoder operates at 10 MHz, and dissipates 147 mW from a single 3.3 V supply.

Difference mode EXELFS with parallel-detection EELS

1992 ◽  
Vol 50 (2) ◽  
pp. 1262-1263
Author(s):  
Michael K. Kundmann ◽  
Ondrej L. Krivanek
Keyword(s):  
Edge Detection ◽  
Important Distinction ◽  
Edge Structure ◽  
Parallel Detection ◽  
Gain Variation ◽  
Ideal Solutions ◽  
Detector Cell ◽  
The Difference ◽  
Elemental Detection ◽  
Partial Correction

Parallel detection has greatly improved the elemental detection sensitivities attainable with EELS. An important element of this advance has been the development of differencing techniques which circumvent limitations imposed by the channel-to-channel gain variation of parallel detectors. The gain variation problem is particularly severe for detection of the subtle post-threshold structure comprising the EXELFS signal. Although correction techniques such as gain averaging or normalization can yield useful EXELFS signals, these are not ideal solutions. The former is a partial throwback to serial detection and the latter can only achieve partial correction because of detector cell inhomogeneities. We consider here the feasibility of using the difference method to efficiently and accurately measure the EXELFS signal.An important distinction between the edge-detection and EXELFS cases lies in the energy-space periodicities which comprise the two signals. Edge detection involves the near-edge structure and its well-defined, shortperiod (5-10 eV) oscillations. On the other hand, EXELFS has continuously changing long-period oscillations (∼10-100 eV).

A Dividing Ratio Changeable Digital PLL Based on Phase State Memory and Double Clock-Edge Detection

2008 ◽  
Vol 128 (7) ◽  
pp. 1185-1190 ◽  
Author(s):  
Kuniaki Fujimoto ◽  
Hirofumi Sasaki ◽  
Mitsutoshi Yahara
Keyword(s):  
Edge Detection ◽  
Phase State

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Leading Edge Detection of RF-Signal for Power Arcing Source Location

2014 ◽  
Vol 9 (5) ◽  
pp. 1060
Author(s):  
Frank Zoko Ble ◽  
Matti Lehtonen ◽  
Ari Sihvola ◽  
Charles Kim
Keyword(s):  
Edge Detection ◽  
Leading Edge ◽  
Source Location ◽  
Rf Signal
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