Wide-band digital down conversion technique based on poly-phase filter

2015 ◽  
Author(s):  
N. Pang ◽  
H.Q. Mu ◽  
P.J. Xu
Keyword(s):  
Wide Band ◽  
Phase Filter ◽  
Digital Down Conversion ◽  
Down Conversion

A High Efficient Baseband GNSS Signal Narrow Band Anti-Jamming Approach in Frequency Domain

2014 ◽  
Vol 926-930 ◽  
pp. 1857-1860
Author(s):  
Zhou Zheng ◽  
Meng Yuan Li ◽  
Wei Jiang Wang
Keyword(s):  
Signal Processing ◽  
Frequency Domain ◽  
Narrow Band ◽  
Low Frequency ◽  
Frequency Resolution ◽  
Interference Rejection ◽  
High Efficient ◽  
Digital Down Conversion ◽  
Down Conversion ◽  
Low Rate

In order to reduce the burden of the calculation and the low frequency resolution of the tradition GNSS signal intermediate narrow band anti-jamming method, it introduces a high efficient approach of narrow band interference rejection based on baseband GNSS signal processing. After digital down conversion to baseband and down sampling to a low rate, the interference is removed in frequency domain. According to the theoretical analysis and simulation, it claims that the method can reduce the calculation and increase the detection resolution in frequency domain which will realize a high efficient interference rejection.

scholarly journals Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio

2018 ◽  
Vol 7 (2.16) ◽  
pp. 88 ◽  
Author(s):  
Latha Sahukar ◽  
Dr M. Madhavi Latha
Keyword(s):  
Cognitive Radio ◽  
Frequency Domain ◽  
Software Defined Radio ◽  
Sampling Rate ◽  
Complex Multiplication ◽  
Clock Rate ◽  
Direct Rotation ◽  
Digital Down Conversion ◽  
Frequency Domain Filtering ◽  
Down Conversion

This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time  occupies  only 10% of the slices of  FPGA. 

Digital down-conversion and up-conversion

2011 ◽  
pp. 333-379
Author(s):  
Yue Zhang ◽  
Taiwen Tang ◽  
Kok-Keong Loo ◽  
Ben Allen ◽  
Dayou Li
Keyword(s):  
Digital Down Conversion ◽  
Down Conversion
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