Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction

2017 ◽  
Vol 26 (1) ◽  
pp. 58-64 ◽  
Author(s):  
Yuanxi Peng ◽  
Jiyang Chen ◽  
Yuanwu Lei ◽  
Tingting He ◽  
Ziye Deng
Keyword(s):  
Low Latency ◽  
Square Root

IEEE-754 Half-Precision Floating-Point Low-Latency Reciprocal Square Root IP-Core

2018 ◽  
Author(s):  
Cuauhtemoc R. Aguilera-Galicia ◽  
Omar Longoria-Gandara ◽  
Oscar A. Guzman-Ramos ◽  
Luis Pizano-Escalante ◽  
Javier Vazouez-Castillo
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Square Root ◽  
Ip Core

On-chip implementation of a low-latency bit-accurate reciprocal square root unit

Integration ◽  
2018 ◽  
Vol 63 ◽  
pp. 9-17 ◽  
Author(s):  
Cuauhtémoc R. Aguilera-Galicia ◽  
Omar Longoria-Gandara ◽  
Luis Pizano-Escalante ◽  
Javier Vázquez-Castillo ◽  
Manuel Salim-Maza
Keyword(s):  
Low Latency ◽  
Square Root ◽  
On Chip

scholarly journals Approximate Square Root Circuits with Low Latency and Power Dissipation

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 46
Author(s):  
Duhwan Kim ◽  
Sunggu Lee
Keyword(s):  
Power Dissipation ◽  
Structural Similarity ◽  
Error Rates ◽  
Low Latency ◽  
Cmos Process ◽  
Square Root ◽  
Low Area ◽  
Image Contrast Enhancement ◽  
User Design ◽  
Power Delay Product

This paper proposes a series of approximate square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of controlled add–subtract cell elements with both exact and approximate versions. The utility of the proposed designs are evaluated by utilizing them in an example image contrast enhancement application with demonstrably satisfactory results and large peak signal-to-noise ratios and structural similarity values. The accuracy and hardware characteristics of the proposed square root designs are also analyzed and compared with previously proposed state-of-the-art approximate square root designs. When applied to a 16-bit radicand (the number under the square root symbol), the proposed designs have the lowest error rates, normalized mean error distances, and mean relative error distances by at least 1.8x when compared to all previous methods using the same number of approximate cells. When the designs were synthesized using Synopsys Design Compiler with a 28 nm bulk CMOS process, the delay, area, power, and power-delay-product characteristics outperform all previous designs in all but a few cases. These results demonstrate that the proposed designs permit the use of a flexible range of approximate designs with varying accuracy and hardware overhead characteristics, and a suitable design can be selected based on the user design requirements.

Small Scale and Low Latency Oriented Neural Network Physical Unclonable Function and its Evaluation

2020 ◽  
Vol 140 (12) ◽  
pp. 1297-1306
Author(s):  
Shu Takemoto ◽  
Kazuya Shibagaki ◽  
Yusuke Nozaki ◽  
Masaya Yoshikawa
Keyword(s):  
Neural Network ◽  
Small Scale ◽  
Low Latency ◽  
Physical Unclonable Function
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