High performance electronic devices based on nanofibers via a crosslinking welding process

Nanoscale ◽  
2018 ◽  
Vol 10 (41) ◽  
pp. 19427-19434 ◽  
Author(s):  
Youchao Cui ◽  
You Meng ◽  
Zhen Wang ◽  
Chunfeng Wang ◽  
Guoxia Liu ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Epoxy Resin ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Electronic Devices ◽  
Welding Process ◽  
Device Performance ◽  
Adhesion Performance

An amine-hardened epoxy resin was selected as adhesion agent to weld nanofiber and improve the adhesion performance, resulting in low contact-resistance nanofiber networks (NFNs). The field-effect transistors based on In2O3 NFNs/SiO2 exhibit high device performance.

scholarly journals High Performance Field-Effect Transistors Based on Partially Suspended 2D Materials via Block Copolymer Lithography

Polymers ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 566
Author(s):  
Simon Kim ◽  
Su Eon Lee ◽  
Jun Hyun Park ◽  
Jin Yong Shin ◽  
Bom Lee ◽  
...  
Keyword(s):  
Block Copolymer ◽  
Self Assembly ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
2D Materials ◽  
Electronic Devices ◽  
Great Promise ◽  
Substrate Effect ◽  
Device Performance

Although various two-dimensional (2D) materials hold great promise in next generation electronic devices, there are many challenges to overcome to be used in practical applications. One of them is the substrate effect, which directly affects the device performance. The large interfacial area and interaction between 2D materials and substrate significantly deteriorate the device performance. Several top-down approaches have been suggested to solve the problem. Unfortunately, however, they have some drawbacks such as a complicated fabrication process, a high production cost, or a poor mechanical property. Here, we suggest the partially suspended 2D materials-based field-effect transistors (FETs) by introducing block copolymer (BCP) lithography to fabricate the substrate effect-free 2D electronic devices. A wide range of nanometer size holes (diameter = 31~43 nm) is successfully realized with a BCP self-assembly nanopatterning process. With this approach, the interaction mechanism between active 2D materials and substrate is elucidated by precisely measuring the device performance at varied feature size. Our strategy can be widely applied to fabricate 2D materials-based high performance electronic, optoelectronic, and energy devices using a versatile self-assembly nanopatterning process.

Sub-5 nm monolayer germanium selenide (GeSe) MOSFETs: towards a high performance and stable device

Nanoscale ◽  
2020 ◽  
Vol 12 (28) ◽  
pp. 15443-15452
Author(s):  
Ying Guo ◽  
Feng Pan ◽  
Gaoyang Zhao ◽  
Yajie Ren ◽  
Binbin Yao ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Device Performance ◽  
Gate Length ◽  
Germanium Selenide ◽  
Technology Roadmap

ML GeSe field-effect transistors have an excellent device performance, even at the 1 nm gate-length. The on-state current of the devices can fulfill the requirements of the International Technology Roadmap for Semiconductors (2013 version).

Organic field-effect transistors integrated with Ti2CTx electrodes

Nanoscale ◽  
2018 ◽  
Vol 10 (11) ◽  
pp. 5191-5197 ◽  
Author(s):  
Shen Lai ◽  
Sung Kyu Jang ◽  
Jeong Ho Cho ◽  
Sungjoo Lee
Keyword(s):  
Contact Resistance ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Device Performance ◽  
Organic Field Effect Transistors

Pentacene organic field-effect transistors integrated with MXene (Ti2CTx) electrodes are studied. Superior device performance with high mobility, high on/off ratio, and low contact resistance is achieved.

scholarly journals Contact Resistance Induced Variability in Graphene Field Effect Transistors

2021 ◽  
Vol 13 (1) ◽  
pp. 153-163
Author(s):  
S. Behera ◽  
S. R. Pattanaik ◽  
G. Dash
Keyword(s):  
Contact Resistance ◽  
Field Effect ◽  
High Performance ◽  
Semiconductor Device ◽  
Field Effect Transistors ◽  
Simulation Method ◽  
Process Variability ◽  
Graphene Field Effect Transistor ◽  
Dual Gate ◽  
Graphene Devices

The success of the graphene field-effect transistor (GFET) is primarily based on solving the problems associated with the growth and transfer of high-quality graphene, the deposition of dielectrics and contact resistance. The contact resistance between graphene and metal electrodes is crucial for the achievement of high-performance graphene devices. This is because process variability is inherent in semiconductor device manufacturing. Two units, even manufactured in the same batch, never show identical characteristics. Therefore, it is imperative that the effect of variability be studied with a view to obtain equivalent performance from similar devices. In this study, we undertake the variability of source and drain contact resistances and their effects on the performance of GFET. For this we have used a simulation method developed by us. The results show that the DC characteristics of GFET are highly dependent on the channel resistance. Also the ambipolar characteristics are strongly affected by the variation of source and drain resistances. We have captured their impact on the output as well as transfer characteristics of a dual gate GFET.

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

Science ◽  
2018 ◽  
Vol 361 (6400) ◽  
pp. 387-392 ◽  
Author(s):  
Chenguang Qiu ◽  
Fei Liu ◽  
Lin Xu ◽  
Bing Deng ◽  
Mengmeng Xiao ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
Electron Density Distribution ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Electronic Devices ◽  
Electronic Switches

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

Self-forming electrode modification in organic field-effect transistors

2016 ◽  
Vol 4 (35) ◽  
pp. 8297-8303 ◽  
Author(s):  
Sangmoo Choi ◽  
Felipe A. Larrain ◽  
Cheng-Yin Wang ◽  
Canek Fuentes-Hernandez ◽  
Wen-Fang Chou ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Spin Coating ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Organic Field Effect Transistors ◽  
Electrode Modification ◽  
Silver Electrodes

High-performance top-gate TIPS-pentacene/PTAA OFETs having low contact resistance were fabricated by mixing PFBT directly into the semiconductor solution and spin-coating the solution on bare silver electrodes.

scholarly journals High performance p-channel transistors on flexible substrate using direct roll transfer stamping

2021 ◽  
Author(s):  
Ayoub Abdulhafith Sadek Zumeit ◽  
Abhishek S Dahiya ◽  
Adamos Christou ◽  
Ravinder Dahiya
Keyword(s):  
High Performance ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Flexible Substrate ◽  
Electronic Devices ◽  
Silicon On Insulator ◽  
Flexible Substrates ◽  
Device Performance ◽  
Mechanical Bending ◽  
P Type

Abstract lexible electronics with high-performance devices is crucial for transformative advances in several emerging and traditional applications. To address this need, herein we present p-type silicon (Si) nanoribbons (NR)-based high-performance field-effect transistors (FETs) developed using innovative Direct Roll Transfer Stamping (DRTS) process. First, ultrathin Si NRs (~70 nm) are obtained from silicon on insulator (SOI) wafers using conventional top-down method, and then DRTS method is employed to directly place the NRs onto flexible substrates at room temperature (RT). The NRFETs are then developed following RT fabrication process which include deposition of high-quality SiNx dielectric. The fabricated p-channel transistors demonstrate high linear mobility ~100±10 cm2/Vs, current on/off ratio >10^4, and low gate leakage (<1nA). Further, the transistors showed robust device performance under mechanical bending and at wide temperature range (15 to 90 °C), showing excellent potential for futuristic high-performance flexible electronic devices/circuits.

scholarly journals Purity of organic semiconductors as a key factor for the performance of organic electronic devices

2020 ◽  
Vol 4 (12) ◽  
pp. 3678-3689
Author(s):  
Cigdem Yumusak ◽  
Niyazi Serdar Sariciftci ◽  
Mihai Irimia-Vladu
Keyword(s):  
Organic Semiconductors ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Electronic Devices ◽  
Organic Field Effect Transistors ◽  
Organic Electronic Devices ◽  
Organic Electronic ◽  
Key Factor ◽  
Key Parameter

Effects of purification were studied in organic field effect transistors. The results presented here indicate that the purity of organic semiconductors is a key parameter to achieve high performance for the field of organic field effect transistors.

scholarly journals Device performance limits and negative capacitance of monolayer GeSe and GeTe tunneling field effect transistors

RSC Advances ◽  
2020 ◽  
Vol 10 (27) ◽  
pp. 16071-16078 ◽  
Author(s):  
Peipei Xu ◽  
Jiakun Liang ◽  
Hong Li ◽  
Fengbin Liu ◽  
Jun Tie ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Device Performance ◽  
Negative Capacitance ◽  
Performance Limits ◽  
Tunneling Field Effect Transistors

The ML GeSe and GeTe NCTFETs fulfill the ITRS low power and high performance devices, respectively, at the “4/3” node range.

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