A large-scale on-chip droplet incubation chamber enables equal microbial culture time

RSC Advances ◽  
2016 ◽  
Vol 6 (25) ◽  
pp. 20516-20519 ◽  
Author(s):  
Jing Dai ◽  
Hyun Soo Kim ◽  
Adrian Ryan Guzman ◽  
Won-Bo Shim ◽  
Arum Han
Keyword(s):  
Incubation Time ◽  
Large Scale ◽  
Microbial Culture ◽  
Culture Time ◽  
Incubation Chamber ◽  
On Chip ◽  
First In First Out

A compact on-chip first-in first-out droplet incubation chamber enables an equal droplet incubation time for a large number of droplets.

scholarly journals Nanolaser-based emulators of spin Hamiltonians

Nanophotonics ◽  
2020 ◽  
Vol 9 (13) ◽  
pp. 4193-4198 ◽  
Author(s):  
Midya Parto ◽  
William E. Hayenga ◽  
Alireza Marandi ◽  
Demetrios N. Christodoulides ◽  
Mercedeh Khajavikhan
Keyword(s):  
Large Scale ◽  
Optimization Problems ◽  
Exchange Interactions ◽  
Np Hard ◽  
Spin Models ◽  
Geometric Frustration ◽  
Spin Hamiltonians ◽  
Hard Problems ◽  
On Chip ◽  
Classical Spin Models

AbstractFinding the solution to a large category of optimization problems, known as the NP-hard class, requires an exponentially increasing solution time using conventional computers. Lately, there has been intense efforts to develop alternative computational methods capable of addressing such tasks. In this regard, spin Hamiltonians, which originally arose in describing exchange interactions in magnetic materials, have recently been pursued as a powerful computational tool. Along these lines, it has been shown that solving NP-hard problems can be effectively mapped into finding the ground state of certain types of classical spin models. Here, we show that arrays of metallic nanolasers provide an ultra-compact, on-chip platform capable of implementing spin models, including the classical Ising and XY Hamiltonians. Various regimes of behavior including ferromagnetic, antiferromagnetic, as well as geometric frustration are observed in these structures. Our work paves the way towards nanoscale spin-emulators that enable efficient modeling of large-scale complex networks.

scholarly journals Simba

2021 ◽  
Vol 64 (6) ◽  
pp. 107-116
Author(s):  
Yakun Sophia Shao ◽  
Jason Cemons ◽  
Rangharajan Venkatesan ◽  
Brian Zimmer ◽  
Matthew Fojtik ◽  
...  
Keyword(s):  
Deep Learning ◽  
Large Scale ◽  
Data Locality ◽  
Coarse Grained ◽  
Batch Size ◽  
Peak Performance ◽  
Large Scale Systems ◽  
High Area ◽  
On Chip ◽  
And Storage

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with finegrained chiplets for deep learning inference, an application domain with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with a batch size of one, delivering an inference latency of 0.50 ms.

scholarly journals Synchrony and pattern formation of coupled genetic oscillators on a chip of artificial cells

2017 ◽  
Vol 114 (44) ◽  
pp. 11609-11614 ◽  
Author(s):  
Alexandra M. Tayar ◽  
Eyal Karzbrun ◽  
Vincent Noireaux ◽  
Roy H. Bar-Ziv
Keyword(s):  
Pattern Formation ◽  
Large Scale ◽  
Reaction Diffusion ◽  
Biochemical Networks ◽  
Artificial Cells ◽  
Diffusion Dynamics ◽  
Oscillatory Reactions ◽  
Potential Applications ◽  
On Chip ◽  
Genetic Oscillators

Understanding how biochemical networks lead to large-scale nonequilibrium self-organization and pattern formation in life is a major challenge, with important implications for the design of programmable synthetic systems. Here, we assembled cell-free genetic oscillators in a spatially distributed system of on-chip DNA compartments as artificial cells, and measured reaction–diffusion dynamics at the single-cell level up to the multicell scale. Using a cell-free gene network we programmed molecular interactions that control the frequency of oscillations, population variability, and dynamical stability. We observed frequency entrainment, synchronized oscillatory reactions and pattern formation in space, as manifestation of collective behavior. The transition to synchrony occurs as the local coupling between compartments strengthens. Spatiotemporal oscillations are induced either by a concentration gradient of a diffusible signal, or by spontaneous symmetry breaking close to a transition from oscillatory to nonoscillatory dynamics. This work offers design principles for programmable biochemical reactions with potential applications to autonomous sensing, distributed computing, and biomedical diagnostics.

scholarly journals Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

2022 ◽  
Vol 15 (2) ◽  
pp. 1-33
Author(s):  
Mikhail Asiatici ◽  
Paolo Ienne
Keyword(s):  
Large Scale ◽  
Sparse Matrix ◽  
Memory Systems ◽  
Graph Analytics ◽  
Matrix Vector Multiplication ◽  
Area Reduction ◽  
Cache Line ◽  
Speed Up ◽  
Memory Accesses ◽  
On Chip

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24× area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

Large-Scale Fabrication of Flexible On-Chip Micro-Supercapacitors by a Mechanical Scribing Process

2018 ◽  
Vol 5 (13) ◽  
pp. 1652-1657 ◽  
Author(s):  
Tingting Huang ◽  
Kai Jiang ◽  
La Li ◽  
Shuai Chen ◽  
Rui Li ◽  
...  
Keyword(s):  
Large Scale ◽  
On Chip
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