In situ surface cleaning on a Ge substrate using TMA and MgCp2for HfO2-based gate oxides

2015 ◽  
Vol 3 (19) ◽  
pp. 4852-4858 ◽  
Author(s):  
Il-Kwon Oh ◽  
Kangsik Kim ◽  
Zonghoon Lee ◽  
Jeong-Gyu Song ◽  
Chang Wan Lee ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Surface Cleaning ◽  
Interface Quality ◽  
Gate Oxides ◽  
Mos Devices

Compared to TMA, MgCp2is an effective remover of Ge oxides with a more stable interface quality resulting in better electrical properties of Ge-based MOS devices.

In situ cleaning effect on the electrical properties of Ge MOS devices by Ar gas anneal

2006 ◽  
Vol 53 (10) ◽  
pp. 2661-2664 ◽  
Author(s):  
Weiping Bai ◽  
Nan Lu ◽  
A.P. Ritenour ◽  
M.L. Lee ◽  
D.A. Antoniadis ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Mos Devices ◽  
Ar Gas

Angle-Resolved Photoemission Study of The Electronic Structures of Auai1 and Ptga2

1998 ◽  
Vol 524 ◽  
Author(s):  
L.-S. Hsu ◽  
J. D. Denlinger ◽  
J. W. Allen
Keyword(s):  
Flat Band ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Depletion Effect ◽  
Polysilicon Films ◽  
Sims Analysis ◽  
Photoemission Study ◽  
Boron Penetration

ABSTRACTIn this work, in-situ doped polysilicon and poly-SiGe films have been used as the gate material for the fabrication of MOS devices to evaluate their respective performances. These films were deposited in an RTCVD system using a Si2H6 and GeH4 gas mixture. MOS capacitors with 45 Å thick gate oxides and polysilicon/poly-SiGe gates were subjected to different anneals to study boron penetration. SIMS analysis and flat band voltage measurements showed much lower boron penetration for devices with poly-SiGe gates than for devices with polysilicon gates. In addition, C-V measurements showed no poly depletion effects for poly-SiGe gates while polysilicon gates had a depletion effect of about 8%. A comparison of resistivities of these films showed a low resistivity of 1 mΩ-cm for poly-SiGe films versus 3 mΩ-cm for polysilicon films after an anneal at 950 °C for 30 seconds.

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces

2015 ◽  
Vol 821-823 ◽  
pp. 480-483 ◽  
Author(s):  
A.I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
V.V. Luchinin ◽  
S.A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Gate Oxides ◽  
Mos Structure ◽  
Mos Devices ◽  
Inversion Channel ◽  
And Inversion ◽  
Thermally Grown

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

Distinguishing various influences on the electrical properties of thin-barrier AlGaN/GaN heterojunctions with in-situ SiN caps

2021 ◽  
Vol 132 ◽  
pp. 105907
Author(s):  
Jiaqi He ◽  
Wei-Chih Cheng ◽  
Yang Jiang ◽  
Mengya Fan ◽  
Guangnan Zhou ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Thin Barrier

scholarly journals Temperature Dependence of Electrical Properties and Crystal Structure of 0.29Pb(In1/2Nb1/2)O3–0.44Pb(Mg1/3Nb2/3)O3–0.27PbTiO3Single Crystals

2013 ◽  
Vol 2013 ◽  
pp. 1-5
Author(s):  
Qian Li ◽  
Yun Liu ◽  
Andrew Studer ◽  
Zhenrong Li ◽  
Ray Withers ◽  
...  
Keyword(s):  
Crystal Structure ◽  
Phase Transition ◽  
Electrical Properties ◽  
Dielectric Permittivity ◽  
Neutron Diffraction ◽  
Electrical Measurement ◽  
Temperature Dependent ◽  
Electromechanical Properties ◽  
Polar Order

We characterized the temperature dependent (~25–200°C) electromechanical properties and crystal structure of Pb(In1/2Nb1/2)O3-Pb(Mg1/3Nb2/3)O3-PbTiO3single crystals usingin situelectrical measurement and neutron diffraction techniques. The results show that the poled crystal experiences an addition phase transition around 120°C whereas such a transition is absent in the unpoled crystal. It is also found that the polar order persists above the maximum dielectric permittivity temperature at which the crystal shows a well-defined antiferroelectric behavior. The changes in the electrical properties and underlying crystal structure are discussed in the paper.

A Comparison of Mos Devices with In-Situ Boron Doped Polysilicon and Poly Sige Gates Deposited in an Rtcvd System Using S12H6 and B2H6 Gas Mixture

1998 ◽  
Vol 525 ◽  
Author(s):  
M. R. Mirabedini ◽  
V. Z-Q Li ◽  
A. R. Acker ◽  
R. T. Kuehn ◽  
D. Venables ◽  
...  
Keyword(s):  
Flat Band ◽  
Gas Mixture ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Boron Doped ◽  
Depletion Effect ◽  
Polysilicon Films ◽  
Sims Analysis ◽  
Boron Penetration

ABSTRACTIn this work, in-situ doped polysilicon and poly-SiGe films have been used as the gate material for the fabrication of MOS devices to evaluate their respective performances. These films were deposited in an RTCVD system using a Si2H6 and GeH4 gas mixture. MOS capacitors with 45 Å thick gate oxides and polysilicon/poly-SiGe gates were subjected to different anneals to study boron penetration. SIMS analysis and flat band voltage measurements showed much lower boron penetration for devices with poly-SiGe gates than for devices with polysilicon gates. In addition, C-V measurements showed no poly depletion effects for poly-SiGe gates while polysilicon gates had a depletion effect of about 8%. A comparison of resistivities of these films showed a low resistivity of 1 mΩ-cm for poly-SiGe films versus 3 mΩ-cm for polysilicon films after an anneal at 950 °C for 30 seconds.

Properties of Thin SiO2 Films with In-Situ Deposition of Poly Si Electrodes

1989 ◽  
Vol 146 ◽  
Author(s):  
Paihung Pan ◽  
Ahmad Kermani ◽  
Wayne Berry ◽  
Jimmy Liao
Keyword(s):  
Electrical Properties ◽  
Breakdown Strength ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
In Situ Deposition ◽  
Different Temperatures ◽  
Flatband Voltage ◽  
Si Films

ABSTRACTElectrical properties of thin (12 nm) SiO2 films with and without in-situ deposited poly Si electrodes have been studied. Thin SiO2 films were grown by the rapid thermal oxidation (RTO) process and the poly Si films were deposited by the rapid thermal chemical vapor deposition (RTCVD) technique at 675°C and 800°C. Good electrical properties were observed for SiO2 films with thin in-situ poly Si deposition; the flatband voltage was ∼ -0.86 V, the interface state density was < 2 × 1010/cm2/eV, and breakdown strength was > 10 MV/cm. The properties of RTCVD poly Si were also studied. The grain size was 10-60 rim before anneal and was 50-120 rim after anneal. Voids were found in thin (< 70 nm) RTCVD poly Si films. No difference in either SiO2 properties or poly Si properties was observed for poly Si films deposited at different temperatures.

How Small Is Too Small ? Understanding The Electronic Structure Of Atomic-Scale Transistors

1999 ◽  
Vol 5 (S2) ◽  
pp. 120-121
Author(s):  
D. A. Muller ◽  
T. Sorsch ◽  
S. Moccio ◽  
F. H. Baumann ◽  
K. Evans-Lutterodt ◽  
...  
Keyword(s):  
Electronic Structure ◽  
Electrical Properties ◽  
Thermal Oxidation ◽  
Electronic Devices ◽  
Local Environment ◽  
Gate Oxide ◽  
Atomic Scale ◽  
Gate Oxides ◽  
Bulk Properties ◽  
Commercial Use

The transistors planned for commercial use ten years from now in many electronic devices will have gate lengths shorter than 130 atoms, gate oxides thinner than 1.2 nm of SiO2 and clock speeds in excess of 10 GHz. It is now technologically possible to produce such transistors with gate oxides only 5 silicon atoms thick[l]. Since at least two of those 5 atoms are not in a local environment similar to either bulk Si or bulk SiO2, the properties of the interface are responsible for a significant fraction of the “bulk” properties of the gate oxide. However the physical (and especially their electrical) properties of the interfacial atoms are very different from .bulk Si or bulk SiO2. Further, roughness on an atomic scale can alter the leakage current by orders of magnitude.In our studies of such devices, we found that thermal oxidation tends to produce Si/SiO2 interfaces with 0.1-0.2 nm rms roughness.

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