A facile route for the fabrication of large-scale gate-all-around nanofluidic field-effect transistors with low leakage current

Lab on a Chip ◽  
2012 ◽  
Vol 12 (14) ◽  
pp. 2568 ◽  
Author(s):  
Sangwoo Shin ◽  
Beom Seok Kim ◽  
Jiwoon Song ◽  
Hwanseong Lee ◽  
Hyung Hee Cho
Keyword(s):  
Leakage Current ◽  
Field Effect ◽  
Large Scale ◽  
Field Effect Transistors ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Facile Route

Low-Leakage-Current Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistor Using p-Type Gate Contact

2006 ◽  
Vol 45 (No. 11) ◽  
pp. L319-L321 ◽  
Author(s):  
Norio Tsuyukuchi ◽  
Kentaro Nagamatsu ◽  
Yoshikazu Hirose ◽  
Motoaki Iwaya ◽  
Satoshi Kamiyama ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Enhancement Mode ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Effect Transistor ◽  
Gan Heterostructure ◽  
P Type

Boosting on Current Using Various Source Material for Dual Gate Tunnel Field Effect Transistor

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Priyadarshini N D ◽  
Nayana G H ◽  
P Vimala
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Source Material ◽  
Oxide Semiconductor ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Dual Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

STUDY OF ORGANIC THIN FILM TRANSISTOR WITH PHOTOPATTERNED GATE DIELECTRIC

2012 ◽  
Vol 26 (31) ◽  
pp. 1250204 ◽  
Author(s):  
HONGGUANG XU ◽  
FENG RAN ◽  
YUAN JI ◽  
JIMEI ZHANG ◽  
WENQING ZHU
Keyword(s):  
Indium Tin Oxide ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Thin Film Transistor ◽  
Organic Thin Film ◽  
Dielectric Thickness ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Ito Glass

In order to investigate the feasibility of gating organic field-effect transistors (OFETs) using a photosensitive photoresist material, pentacene-based OFETs were fabricated on indium tin oxide (ITO) glass. The gate dielectric was found to be easily patterned by spin coating and UV exposure, and has an excellent surface roughness of 0.22 nm and good insulating properties, resulting in a low leakage current (49 nA at 2 MV/cm) at a dielectric thickness of 290 nm. The OFET with photopatterned gate dielectric exhibited good electric characteristics, including a high field-effect mobility of 0.15 cm2/Vs, a threshold voltage of -9.9 V, and on/off current ratio of ~104. The high matching of surface free energy between the gate dielectric and pentacene is proved to be contributed to the good performance of the device.

High nonlinearity and low leakage current SnO2 varistor ceramics by co-doping with yttrium and tantalum

2021 ◽  
Vol 285 ◽  
pp. 129120
Author(s):  
Wenxin Liang ◽  
Hongfeng Zhao ◽  
Xiaoji Meng ◽  
Shaohua Fan ◽  
Qingyun Xie
Keyword(s):  
Leakage Current ◽  
Co Doping ◽  
High Nonlinearity ◽  
Low Leakage ◽  
Low Leakage Current

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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