Development of a contactless conductivity detector cell for 1.6 mm O.D. (1/16th inch) HPLC tubing and micro-bore columns with on-column detection

The Analyst ◽  
2008 ◽  
Vol 133 (8) ◽  
pp. 1104 ◽  
Author(s):  
Eoin Gillespie ◽  
Damian Connolly ◽  
Mirek Macka ◽  
Peter Hauser ◽  
Brett Paull
Keyword(s):  
Author(s):  
Michael K. Kundmann ◽  
Ondrej L. Krivanek

Parallel detection has greatly improved the elemental detection sensitivities attainable with EELS. An important element of this advance has been the development of differencing techniques which circumvent limitations imposed by the channel-to-channel gain variation of parallel detectors. The gain variation problem is particularly severe for detection of the subtle post-threshold structure comprising the EXELFS signal. Although correction techniques such as gain averaging or normalization can yield useful EXELFS signals, these are not ideal solutions. The former is a partial throwback to serial detection and the latter can only achieve partial correction because of detector cell inhomogeneities. We consider here the feasibility of using the difference method to efficiently and accurately measure the EXELFS signal.An important distinction between the edge-detection and EXELFS cases lies in the energy-space periodicities which comprise the two signals. Edge detection involves the near-edge structure and its well-defined, shortperiod (5-10 eV) oscillations. On the other hand, EXELFS has continuously changing long-period oscillations (∼10-100 eV).


2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Janez Puhan ◽  
Dušan Raič ◽  
Tadej Tuma ◽  
Árpád Bűrmen

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.


The Analyst ◽  
1990 ◽  
Vol 115 (9) ◽  
pp. 1247 ◽  
Author(s):  
Liliana Ilieva Ilcheva ◽  
Anastas Dimitrou Dakashev
Keyword(s):  

1974 ◽  
Vol 46 (6) ◽  
pp. 755-757 ◽  
Author(s):  
James F. Lawrence ◽  
Alan H. Moore

2016 ◽  
Vol 15 (3) ◽  
pp. 356-366 ◽  
Author(s):  
Hamidreza Aghasi ◽  
Rouhollah Mousavi Iraei ◽  
Azad Naeemi ◽  
Ehsan Afshari

1975 ◽  
Vol 107 (1) ◽  
pp. 193-195 ◽  
Author(s):  
Matilda Jernjčič ◽  
Miha Kremser ◽  
Marko Razinger

1966 ◽  
Vol 4 (9) ◽  
pp. 353-354 ◽  
Author(s):  
D. R. A. Wharton ◽  
M. Bazinet ◽  
M. L. Wharton
Keyword(s):  

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