Fast Switching Water Processable Electrochromic Polymers

2012 ◽  
Vol 4 (12) ◽  
pp. 6512-6521 ◽  
Author(s):  
Pengjie Shi ◽  
Chad M. Amb ◽  
Aubrey L. Dyer ◽  
John R. Reynolds
2015 ◽  
Vol 39 (7) ◽  
pp. 5389-5394 ◽  
Author(s):  
Xiaoming Chen ◽  
Zhangping Xu ◽  
Sai Mi ◽  
Jianming Zheng ◽  
Chunye Xu

The introduction of a thiophene unit in red-to-transmissive electrochromic polymers successfully improves the switching speed (t95 = 1.6 s).


2016 ◽  
Vol 4 (12) ◽  
pp. 2269-2273 ◽  
Author(s):  
Hongtao Yu ◽  
Shan Shao ◽  
Lijia Yan ◽  
Hong Meng ◽  
Yaowu He ◽  
...  

The synthesised electrochromic polymers can exhibit a vegetable-green color at lower applied voltages and a soil-brown color in the oxidized-state, excellent solubility, superhydrophobicity, strong absorption, very fast switching times, and high stability.


2020 ◽  
Vol 140 (6) ◽  
pp. 488-494
Author(s):  
Haruo Naitoh ◽  
Takaya Sugimoto ◽  
Keisuke Fujisaki
Keyword(s):  

Author(s):  
Bhanu P. Sood ◽  
Michael Pecht ◽  
John Miker ◽  
Tom Wanek

Abstract Schottky diodes are semiconductor switching devices with low forward voltage drops and very fast switching speeds. This paper provides an overview of the common failure modes in Schottky diodes and corresponding failure mechanisms associated with each failure mode. Results of material level evaluation on diodes and packages as well as manufacturing and assembly processes are analyzed to identify a set of possible failure sites with associated failure modes, mechanisms, and causes. A case study is then presented to illustrate the application of a systematic FMMEA methodology to the analysis of a specific failure in a Schottky diode package.


2020 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pengfei Zhou ◽  
Jason Eshraghian ◽  
Chih-Yang Lin ◽  
Herbert Ho-Ching Iu ◽  
...  

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>


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