High-k Dielectric Passivation: Novel Considerations Enabling Cell Specific Lysis Induced by Electric Fields

2016 ◽  
Vol 8 (33) ◽  
pp. 21228-21235 ◽  
Author(s):  
Klemens J. Wassermann ◽  
Sven Barth ◽  
Franz Keplinger ◽  
Christa Noehammer ◽  
Johannes R. Peham
2019 ◽  
Author(s):  
Terje Wimberger ◽  
Verena K. Köhler ◽  
Eva K. Ehmoser ◽  
Klemens J. Wassermann

AbstractIrreversible electroporation holds great potential for cell-specific lysis due to the size-dependent susceptibility of cells to externally imposed electric fields. Previous attempts at selective cell lysis lead to significant overlap between affected populations and struggle with inconsistent biological outcome. We propose that charge transfer at the electrode-liquid interface is responsible by inducing multifactorial effects originating from both the electric field and electrochemical reactions. A promising remedy is the coating of electrodes with a high-k dielectric layer. The resulting capacitive coupling restores the selective potential of electric field mediated lysis in a microfluidic setup. Initial experiments show the consistent depletion of erythrocytes from whole blood while leaving leukocytes intact. The same is true for the reproducible and selective depletion of Jurkat and MCF-7 cells in a mixture with leukocytes. Unexpectedly, the observed order of lysis cannot be correlated with cell size. This implies that the cellular response to capacitive coupling features a selective characteristic that is different from conventional lysis configurations.


2002 ◽  
Vol 716 ◽  
Author(s):  
Pallavi Krishnamoorthi ◽  
A N Chandorkar

AbstractTantalum Pentaoxide, an alternative to SiO2, as a high-k dielectric for DRAM and MOS applications, faces the problem of interface mismatch at silicon. SiO2 or Si3N4 interfacial layer could help in overcoming this problem. The higher band offsets of these materials also help in the reduction of leakage currents at low electric fields. Here we study the physical and electrical characteristics of Ta, oxidized in O2:NH3 ambient, and without any other interface layer. This is done to check if N/H moves to the interface, and thus improves the electrical properties. XRD studies of the film, showed the presence of Ta2O5. Peaks corresponding to TaSi2, un-oxidized tantalum and TaN were also found in the film. But the intensity of these peaks decreased with the reduction of NH3 content. Thus a higher oxygen content could reduce the content of TaN and unoxidized tantalum. FTIR analysis however showed strong Ta=O and Si-O peaks. For the MOS capacitors, due to the presence of resistive components, the maximum capacitance was reduced, compared to that of pure Ta2O5 films. Oxide charges in the films were observed to be around 1.9E10 cm-2. But the traps in these films were found to be almost negligible as observed from the negligible hysteresis in the C-V characteristics. Films with N/H showed lesser oxide charges by an order of magnitude, as compared to pure Ta2O5 films.


2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.


2012 ◽  
Vol 29 (5) ◽  
pp. 057702 ◽  
Author(s):  
Yue-Chan Kong ◽  
Fang-Shi Xue ◽  
Jian-Jun Zhou ◽  
Liang Li ◽  
Chen Chen ◽  
...  

2012 ◽  
Vol 45 (3) ◽  
pp. 537-542 ◽  
Author(s):  
C.-Y. Wu ◽  
P.-Y. Hsu ◽  
C. L. Wang ◽  
T.-C. Liao ◽  
H.-C. Cheng ◽  
...  

2017 ◽  
Vol 897 ◽  
pp. 571-574 ◽  
Author(s):  
Vidya Naidu ◽  
Sivaprasad Kotamraju

Silicon Carbide (SiC) based MOS devices are one of the promising devices for high temperature, high switching frequency and high power applications. In this paper, the static and dynamic characteristics of an asymmetric trench gate SiC IGBT with high-k dielectrics- HfO2 and ZrO2 are investigated. SiC IGBT with HfO2 and ZrO2 exhibited higher forward transconductance ratio and lower threshold voltage compared to conventionally used SiO2. In addition, lower switching power losses have been observed in the case of high-k dielectrics due to reduced tail current duration.


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