Solution-Gated Ultrathin Channel Indium Tin Oxide-Based Field-Effect Transistor Fabricated by a One-Step Procedure that Enables High-Performance Ion Sensing and Biosensing

2021 ◽  
Author(s):  
Toshiya Sakata ◽  
Shoichi Nishitani ◽  
Akiko Saito ◽  
Yuta Fukasawa
Keyword(s):  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Ion Sensing ◽  
Step Procedure ◽  
One Step ◽  
Effect Transistor

Reduced graphene oxide field-effect transistor with indium tin oxide extended gate for proton sensing

2014 ◽  
Vol 14 (5) ◽  
pp. 738-743 ◽  
Author(s):  
Thuy Kieu Truong ◽  
T.N.T. Nguyen ◽  
Tran Quang Trung ◽  
Il Yung Sohn ◽  
Duck-Jin Kim ◽  
...  
Keyword(s):  
Graphene Oxide ◽  
Reduced Graphene Oxide ◽  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Reduced Graphene ◽  
Effect Transistor

scholarly journals Indium tin oxide coated PET for differential pH‐sensing using field‐effect transistor based sensor

2018 ◽  
Vol 13 (11) ◽  
pp. 1525-1530 ◽  
Author(s):  
Naser Mokhtarifar ◽  
Frank Goldschmidtboeing ◽  
Peter Woias
Keyword(s):  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ph Sensing ◽  
Effect Transistor

One-step fabrication of CdS:Mo–CdMoO4core–shell nanoribbons for nonvolatile memory devices with high resistance switching

2017 ◽  
Vol 5 (25) ◽  
pp. 6156-6162 ◽  
Author(s):  
Ni Zheng ◽  
Zhibin Shao ◽  
Feifei Xia ◽  
Tianhao Jiang ◽  
Xiaofeng Wu ◽  
...  
Keyword(s):  
High Resistance ◽  
Nonvolatile Memory ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Core Shell ◽  
Memory Devices ◽  
Nonvolatile Memory Devices ◽  
One Step ◽  
Effect Transistor

A one-step fabrication of CdS:Mo–CdMoO4core–shell nanoribbons (NR) was achieved for applications in high performance nano-field-effect transistor (FET)-based nonvolatile memory (NVM) device.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

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