Fully Integrated On-Chip Electrochemical Detection for Capillary Electrophoresis in a Microfabricated Device

2002 ◽  
Vol 74 (15) ◽  
pp. 3690-3697 ◽  
Author(s):  
Richard P. Baldwin ◽  
Thomas J. Roussel, ◽  
Mark M. Crain ◽  
Vijay Bathlagunda ◽  
Douglas J. Jackson ◽  
...  
Keyword(s):  
Capillary Electrophoresis ◽  
Electrochemical Detection ◽  
Fully Integrated ◽  
On Chip

A Capillary Electrophoresis Platform With “On-Chip” Electrochemical Detection: Experimental and Computational Flow Studies

2001 ◽  
Author(s):  
Thomas J. Roussel ◽  
Robert S. Keynton ◽  
Kevin M. Walsh ◽  
Mark M. Crain ◽  
John F. Naber ◽  
...  
Keyword(s):  
Capillary Electrophoresis ◽  
Electrochemical Detection ◽  
Power Supply ◽  
Electroosmotic Flow ◽  
Plug Flow ◽  
Finite Element Models ◽  
Separation Channel ◽  
Flow Models ◽  
On Chip ◽  
Electrochemical Potentials

Abstract The purpose of this study was to compare experimental electrokinetic plug flow velocities to computational flow models of microfabricated capillaries. Electroosmotic flow studies of dichlorofluorescein and electrophoretic separation of dopamine and catechol in a microfabricated capillary electrophoresis (CE) system were performed both experimentally and computationally. A “balanced cross design” consisting of a bent 2 cm long injection channel and a straight 2 cm long separation channel was used. The geometry of the capillary was 65 μm wide and 20 μm deep. For the fluorescein study, separation voltages ranging between 0.25 kV and 1 kV were applied, while voltages ranging from 100 V to 550 V were used in the separation studies. Laser Induced Fluorescent (LIF) images were obtained for flow visualization and qualitative analysis in the electroosmotic flow studies, while electrochemical potentials were acquired using “on-chip” electrodes interfaced to a custom-designed power supply and electrochemical detection (ECD) circuit. Finite element models of the experimental device were generated and flows were simulated using commercially available software. For the electroosmotic flow studies, the computational results were found to be within ± 11% of the experimentally obtained values. Similarly, the results of the computational separations of catechol and dopamine predicted plug velocities that were within ± 7.6% of the experimentally determined values.

CMOS fully-integrated wireless temperature sensors with on-chip antenna

2009 ◽  
Author(s):  
Fabio Aquilino ◽  
Francesco G. Della Corte ◽  
Letizia Fragomeni ◽  
Massimo Merenda ◽  
Fabio Zito
Keyword(s):  
Temperature Sensors ◽  
Fully Integrated ◽  
On Chip Antenna ◽  
On Chip

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Process Variations ◽  
Calibration Method ◽  
Capacitance Measurement ◽  
Effective Technique ◽  
Fully Integrated ◽  
Front End ◽  
Novel Method ◽  
On Chip

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

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