Thermomechanical and viscoelastic behavior of a no-flow underfill material for flip-chip applications

2005 ◽  
Vol 439 (1-2) ◽  
pp. 127-134 ◽  
Author(s):  
Yi He
Keyword(s):  
Flip Chip ◽  
Viscoelastic Behavior ◽  
Underfill Material

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

The effect of PECVD SiNxmoisture barrier layers on the degradation of a flip chip underfill material

2001 ◽  
Vol 13 (3) ◽  
pp. 12-15 ◽  
Author(s):  
G. Kaltenpoth ◽  
W. Siebert ◽  
X‐M. Xie ◽  
F. Stubhan
Keyword(s):  
Flip Chip ◽  
Barrier Layers ◽  
Underfill Material

Modeling of Underfilled PBGA Assemblies Using Both Viscoelastic and Elastic Material Properties

2019 ◽  
Author(s):  
Promod R. Chowdhury ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Viscoelastic Properties ◽  
Computational Cost ◽  
Viscoelastic Behavior ◽  
Polymer Materials ◽  
Temperature Dependent ◽  
Solder Joint Fatigue ◽  
Underfill Material

Abstract In microelectronics packaging industry, polymer based materials are used extensively. These polymer materials show viscoelastic behavior when subject to time dependent loads or deformations. The viscoelastic behavior highly depends on both temperature and time. In many cases, these viscoelastic properties are often neglected due to saving computational cost or unavailability of full characterization of the viscoelastic properties. To make accurate predictions of packaging mechanical behavior and reliability, it is important to accurately characterize the viscoelastic behavior of mold compounds, underfill encapsulants, adhesives and other polymers used in electronic assemblies. After characterization, these parameters can be used as input material property data for finite element analysis (FEA) simulations. In this study, both frequency dependent dynamic mechanical analysis (DMA) measurements, and strain and temperature dependent stress relaxation experiments were performed on a typical underfill material in order to characterize its linear viscoelastic behavior. In both cases, a master curve was determined using the assumption of time-temperature equivalence, and Prony series expansions were utilized to model the underfill material relaxation behavior. After that, these viscoelastic underfill material parameters were used in finite element models of underfilled ball grid array packages (Ultra CSP) subjected to thermal cycling from −40 to 125 °C. Separate simulations were also performed using temperature dependent elastic properties for the underfill material. In both cases, the solder joint fatigue life was estimated, and the effects of using viscoelastic properties for the underfill in solder joint fatigue life simulation were investigated.

Flip Chip Underfill RF Characterization

2019 ◽  
Vol 2019 (1) ◽  
pp. 000243-000247
Author(s):  
Robert B. Paul ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Flip Chip ◽  
Power Integrity ◽  
Cavity Resonators ◽  
Dielectric Characterization ◽  
Noise Coupling ◽  
Solder Bumps ◽  
Underfill Material

Abstract To develop reliable high-speed packages, characterization of the underfill material used in the flip-chip process has become of greater importance. The underfill, typically an epoxy resin-based material, offers thermal and structural benefits for the integrated circuit (IC) on package. With so many inputs and outputs (IOs) in close proximity to one another, the integrated circuits on package can have unexpected signal and power integrity issues. Furthermore, chip packages can support signals only up to the frequency where noise coupling (e.g., crosstalk, switching noise, etc.) leads to the malfunctioning of the system. Vertical interconnects, such as vias and solder bumps, are major sources of noise coupling. Inserting ground references between every signal net is not practical. For the solder bumps, the noise coupling depends on the permittivity of the underfill material. Therefore, characterizing the permittivity of the underfill material helps in predicting signal and power integrity issues. Such liquid or semi-viscous materials are commonly characterized from a simple fringe capacitance model of an open-ended coaxial probe immersed in the material. The open-ended coaxial method, however, is not as accurate as resonator-based methods. There is a need for a methodology to accurately extract the permittivity of liquid or semi-viscous materials at high frequencies. The proposed method uses solid walled cavity resonators, where the resonator is filled with the underfill material and cured. Dielectric characterization is a complex process, where the physical characteristics of the cavities must be known or accurately measured. This includes the conductivity of the conductors, roughness of the conductors, the dimensions of the cavity, and the port pin locations. This paper discusses some of the challenges that are encountered when characterizing dielectrics with cavity resonators. This characterization methodology can also be used to characterize other materials of interest.

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