scholarly journals A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

2017 ◽  
Vol 74 ◽  
pp. 1-13 ◽  
Author(s):  
Rasmus Bo Sørensen ◽  
Luca Pezzarossa ◽  
Martin Schoeberl ◽  
Jens Sparsø
Keyword(s):  
Network Interface ◽  
Low Latency ◽  
Time Division Multiplexing ◽  
Networks On Chip ◽  
Virtual Circuits ◽  
On Chip ◽  
Time Division

Design and implementation of low latency network interface for network on chip

2010 ◽  
Author(s):  
Brahim Attia ◽  
Wissem Chouchene ◽  
Abdelkrim Zitouni ◽  
Abid Nourdin ◽  
Rached Tourki
Keyword(s):  
Network On Chip ◽  
Network Interface ◽  
Low Latency ◽  
Design And Implementation ◽  
On Chip

Cluster Based Networks-on-Chip

2013 ◽  
Vol 4 (3) ◽  
pp. 25-41
Author(s):  
Khalid Latif ◽  
Amir-Mohammad Rahmani ◽  
Tiberiu Seceleanu ◽  
Hannu Tenhunen
Keyword(s):  
Critical Path ◽  
Network Interface ◽  
Path Delay ◽  
Traffic Patterns ◽  
Hop Count ◽  
Networks On Chip ◽  
Routing Strategy ◽  
Negative Exponential Distribution ◽  
On Chip ◽  
Negative Exponential

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors

2011 ◽  
Vol 71 (5) ◽  
pp. 641-650 ◽  
Author(s):  
Gilbert Hendry ◽  
Eric Robinson ◽  
Vitaliy Gleyzer ◽  
Johnnie Chan ◽  
Luca P. Carloni ◽  
...  
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Networks On Chip ◽  
On Chip ◽  
Time Division
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