3D analytical model for the SOI LDMOS with alternating silicon and high-k dielectric pillars

2016 ◽  
Vol 96 ◽  
pp. 95-103 ◽  
Author(s):  
Jia-fei Yao ◽  
Yu-feng Guo ◽  
Tian Xia ◽  
Jun Zhang ◽  
Hong Lin
Keyword(s):  
Analytical Model ◽  
High K ◽  
High K Dielectric

scholarly journals Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-${k}$ Dielectric

2019 ◽  
Vol 66 (7) ◽  
pp. 3055-3059 ◽  
Author(s):  
Jiafei Yao ◽  
Yufeng Guo ◽  
Kemeng Yang ◽  
Lin Du ◽  
Jun Zhang ◽  
...  
Keyword(s):  
Analytical Model ◽  
Power Device ◽  
Step Width ◽  
High K ◽  
High K Dielectric

scholarly journals High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashishath ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Figure Of Merit ◽  
Double Gate ◽  
Short Channel ◽  
Ultra Low Power ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric

Abstract This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

scholarly journals Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric

2010 ◽  
Vol 59 (11) ◽  
pp. 8131
Author(s):  
Li Jin ◽  
Liu Hong-Xia ◽  
Li Bin ◽  
Cao Lei ◽  
Yuan Bo
Keyword(s):  
Analytical Model ◽  
Threshold Voltage ◽  
Strained Si ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric

The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High-k Dielectric Pillar

2020 ◽  
Vol 67 (4) ◽  
pp. 1745-1750
Author(s):  
Ling Du ◽  
Yufeng Guo ◽  
Jun Zhang ◽  
Jiafei Yao ◽  
Kemeng Yang ◽  
...  
Keyword(s):  
Analytical Model ◽  
High Voltage ◽  
High K ◽  
High K Dielectric

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

A Substitution for the High- k Dielectric in an AlGaN/GaN Metal-insulator-Semiconductor Heterostructure

2012 ◽  
Vol 29 (5) ◽  
pp. 057702 ◽  
Author(s):  
Yue-Chan Kong ◽  
Fang-Shi Xue ◽  
Jian-Jun Zhou ◽  
Liang Li ◽  
Chen Chen ◽  
...  
Keyword(s):  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Semiconductor Heterostructure ◽  
High K ◽  
High K Dielectric
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