scholarly journals High Performance Dense Linear System Solver with Resilience to Multiple Soft Errors

2012 ◽  
Vol 9 ◽  
pp. 216-225 ◽  
Author(s):  
Peng Du ◽  
Piotr Luszczek ◽  
Jack Dongarra
Keyword(s):  
Linear System ◽  
High Performance ◽  
Soft Errors ◽  
Dense Linear System

scholarly journals Balancing Energy and Performance in Dense Linear System Solvers for Hybrid ARM+GPU platforms

2016 ◽  
Author(s):  
Juan P. Silva ◽  
Ernesto Dufrechou ◽  
Pabl Ezzatti ◽  
Enrique S. Quintana-Ortí ◽  
Alfredo Remón ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Linear System ◽  
Energy Efficient ◽  
High Performance ◽  
Energy Aware ◽  
Balancing Energy ◽  
Dense Linear System ◽  
And Performance ◽  
Hardware Platforms ◽  
Time And Energy

The high performance computing community has traditionally focused uniquely on the reduction of execution time, though in the last years, the optimization of energy consumption has become a main issue. A reduction of energy usage without a degradation of performance requires the adoption of energy-efficient hardware platforms accompanied by the development of energy-aware algorithms and computational kernels. The solution of linear systems is a key operation for many scientific and engineering problems. Its relevance has motivated an important amount of work, and consequently, it is possible to find high performance solvers for a wide variety of hardware platforms. In this work, we aim to develop a high performance and energy-efficient linear system solver. In particular, we develop two solvers for a low-power CPU-GPU platform, the NVIDIA Jetson TK1. These solvers implement the Gauss-Huard algorithm yielding an efficient usage of the target hardware as well as an efficient memory access. The experimental evaluation shows that the novel proposal reports important savings in both time and energy-consumption when compared with the state-of-the-art solvers of the platform.

Analyzing the Robustness of HPC Applications Using a Fine-Grained Soft Error Fault Injection Tool

2016 ◽  
pp. 277-305
Author(s):  
Qiang Guan ◽  
Nathan DeBardeleben ◽  
Sean Blanchard ◽  
Song Fu ◽  
Claude H. Davis IV ◽  
...  
Keyword(s):  
High Performance ◽  
Fault Injection ◽  
Soft Errors ◽  
Small Degree ◽  
Soft Error ◽  
Power Efficient ◽  
Fine Grained ◽  
Different Characteristics ◽  
The Impact ◽  
Performance Computing

As the high performance computing (HPC) community continues to push towards exascale computing, HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. We utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. We demonstrate use cases of F-SEFI on several benchmark applications with different characteristics to show how data corruption can propagate to incorrect results. The findings from the fault injection campaign can be used for designing robust software and power-efficient hardware.

scholarly journals New iterative methods for dense linear systems

2021 ◽  
Vol 293 ◽  
pp. 02013
Author(s):  
Jinmei Wang ◽  
Lizi Yin ◽  
Ke Wang
Keyword(s):  
Linear System ◽  
Linear Systems ◽  
Iterative Methods ◽  
Parallel Implementation ◽  
System Of Equations ◽  
Systems Of Equations ◽  
Linear System Of Equations ◽  
Dense Linear System ◽  
Linear Systems Of Equations

Solving dense linear systems of equations is quite time consuming and requires an efficient parallel implementation on powerful supercomputers. Du, Zheng and Wang presented some new iterative methods for linear systems [Journal of Applied Analysis and Computation, 2011, 1(3): 351-360]. This paper shows that their methods are suitable for solving dense linear system of equations, compared with the classical Jacobi and Gauss-Seidel iterative methods.

scholarly journals High Performance Iterative Solver for Linear System using Multi GPU

2011 ◽  
Vol 6 ◽  
pp. 2401069-2401069 ◽  
Author(s):  
Soichiro IKUNO ◽  
Norihisa FUJITA ◽  
Yuki KAWAGUCHI ◽  
Taku ITOH ◽  
Susumu NAKATA ◽  
...  
Keyword(s):  
Linear System ◽  
High Performance ◽  
Iterative Solver

Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory

SPIN ◽  
2019 ◽  
Vol 09 (01) ◽  
pp. 1950007 ◽  
Author(s):  
Abdolah Amirany ◽  
Ramin Rajaei
Keyword(s):  
High Performance ◽  
Soft Errors ◽  
Magnetic Tunnel Junction ◽  
High Volume ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Volume Data ◽  
Single Node ◽  
Radiation Induced

As CMOS technology scales down toward below 2-digit nanometer dimensions, exponentially increasing leakage power, vulnerability to radiation induced soft errors have become a major problem in today’s logic circuits. Emerging spin-based logic circuits and architectures based on nonvolatile magnetic tunnel junction (MTJ) cells show a great potential to overcome the aforementioned issues. However, radiation induced soft errors are still a problem in MTJ-based circuits as they need sequential peripheral CMOS circuits for sensing the MTJs. This paper proposes a novel nonvolatile and low-cost radiation hardened magnetic full adder (MFA). In comparison with the previous designs, the proposed MFA is capable of tolerating particle strikes regardless of the amount of charge induced to a single node and even multiple nodes. Besides, the proposed MFA offers low power operation, low area and high performance as compared with previous counterparts. One of the most important features suggested by the proposed MFA circuit is full nonvolatility. Nonvolatile logic circuits remove the cost of high volume data transactions between memory and logic and also facilitate power gating in logic-in-memory architectures.

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