Synthesis of highly dense and vertically aligned array of SWCNTs using a catalyst barrier layer: High performance field emitters for devices

2018 ◽  
Vol 550 ◽  
pp. 15-20 ◽  
Author(s):  
Shama Parveen ◽  
Avshish Kumar ◽  
Samina Husain ◽  
Mohammad Zulfequar ◽  
Mushahid Husain
Keyword(s):  
Barrier Layer ◽  
High Performance ◽  
Field Emitters ◽  
Vertically Aligned ◽  
Aligned Array

Characterization of Metallically Bonded Carbon Nanotube-Based Thermal Interface Materials Using a High Accuracy 1D Steady-State Technique

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Joseph R. Wasniewski ◽  
David H. Altman ◽  
Stephen L. Hodson ◽  
Timothy S. Fisher ◽  
Anuradha Bulusu ◽  
...  
Keyword(s):  
Steady State ◽  
High Performance ◽  
Applied Pressure ◽  
Test Facility ◽  
Thermal Interface Materials ◽  
Thermal Interface ◽  
Thermal Interface Resistance ◽  
Vertically Aligned ◽  
Performance Results ◽  
Interface Materials

The next generation of thermal interface materials (TIMs) are currently being developed to meet the increasing demands of high-powered semiconductor devices. In particular, a variety of nanostructured materials, such as carbon nanotubes (CNTs), are interesting due to their ability to provide low resistance heat transport from device-to-spreader and compliance between materials with dissimilar coefficients of thermal expansion (CTEs), but few application-ready configurations have been produced and tested. Recently, we have undertaken major efforts to develop functional nanothermal interface materials (nTIMs) based on short, vertically aligned CNTs grown on both sides of a thin interposer foil and interfaced with substrate materials via metallic bonding. A high-precision 1D steady-state test facility has been utilized to measure the performance of nTIM samples, and more importantly, to correlate performance to the controllable parameters. In this paper, we describe our material structures and the myriad permutations of parameters that have been investigated in their design. We report these nTIM thermal performance results, which include a best to-date thermal interface resistance measurement of 3.5 mm2 K/W, independent of applied pressure. This value is significantly better than a variety of commercially available, high-performance thermal pads and greases we tested, and compares favorably with the best results reported for CNT-based materials in an application-representative setting.

Vertically aligned self-assembled gold nanorods as low turn-on, stable field emitters

2015 ◽  
Vol 355 ◽  
pp. 978-983 ◽  
Author(s):  
Amey Apte ◽  
Padmashree Joshi ◽  
Prashant Bhaskar ◽  
Dilip Joag ◽  
Sulabha Kulkarni
Keyword(s):  
Gold Nanorods ◽  
Turn On ◽  
Field Emitters ◽  
Vertically Aligned ◽  
Self Assembled ◽  
Stable Field

scholarly journals High-Performance Flexible All-Solid-State Asymmetric Supercapacitors Based on Vertically Aligned CuSe@Co(OH)2 Nanosheet Arrays

2018 ◽  
Vol 122 (4) ◽  
pp. 2002-2011 ◽  
Author(s):  
Jiangfeng Gong ◽  
Yazhou Tian ◽  
Ziyuan Yang ◽  
Qianjin Wang ◽  
Xihao Hong ◽  
...  
Keyword(s):  
Solid State ◽  
High Performance ◽  
Asymmetric Supercapacitors ◽  
Nanosheet Arrays ◽  
Vertically Aligned

Optimized TSV Module for High Performance 2.5D Device Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000737-000767
Author(s):  
Cyprian Uzoh ◽  
Liang Wang ◽  
Zhuowen Sun ◽  
Andrew Cao ◽  
Bong-Sub Lee ◽  
...  
Keyword(s):  
Barrier Layer ◽  
High Performance ◽  
Impurity Content ◽  
Electrical Performance ◽  
Reduced Form ◽  
Sidewall Roughness ◽  
Factors Affecting ◽  
Wide Range ◽  
Silicon Vias ◽  
Module Development

3D-IC has been increasingly adopted by the industry owing to its promise of higher device speed and package bandwidth, improved power consumption, reduced form factor, and lower cost for important applications over a wide range of industrial segments including image sensors, logic-memory and logic-logic integration, MEMS, integrated optical interposers and LEDs. This presentation is a systematic study of multiple experimental factors affecting the electrical performance, reliability and scalability of TSVs. Electrical modeling and simulation was used to determine the key factors influencing singal transmission and return losses in TSVs at high (>1 GHz) frequencies. A variety of process modules and steps for the fabrication of through silicon vias were then systematically optimized to ensure high performance. The modules evaluated include TSV etch, TSV fill, chemical mechanical polishing (CMP), pad finish, bonding schemes, wafer thinning, via reveal, passivation, wiring and bumping. One example is the improvement of TSV profile and sidewall roughness through the optimization of DRIE parameters and wet chemical methods to reduce silicon sidewall roughness from that of a typical Bosch etch to less than 10nm which is critical for adhesion of barrier/seed layer and the final reliability of 2.5D packaging. Scalability of void-free via fill process with respect to TSV diameter and depth was addressed by using highly conformal barrier layers. Adhesion of Cu to the barrier layer was also improved upon detailed analysis to prevent delamination and improve reliability. A bottom up plating chemistry with significantly low impurity content was utilized to mitigate voids, seams and excessive overburden in the TSV. Its impact on stress and delamination issues and subsequent reliability failures was studied in details. The annealing process following TSV formation is systematically studied with varying conditions and characterized with metrology and electrical tests to investigate its effect on microstructure and material properties. The process parameters were tuned for CMP of Cu, adhesion and barrier layer without causing corrosion or delamination between adjacent layers. Process requirements for these modules in TSV process are closely related. This presentation will review the process module development in the context of their effects on the integrated TSV parameters (performance, reliability and scalability). We will also provide an in-depth discussion on process module optimization, electrical and mechanical characterization and cost reduction methodologies.

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