A measurement of the photon detection efficiency of silicon photomultipliers

Author(s):  
A.N. Otte ◽  
J. Hose ◽  
R. Mirzoyan ◽  
A. Romaszkiewicz ◽  
M. Teshima ◽  
...  
2022 ◽  
Vol 17 (01) ◽  
pp. C01001
Author(s):  
F. Ahmadov ◽  
G. Ahmadov ◽  
R. Akbarov ◽  
A. Aktag ◽  
E. Budak ◽  
...  

Abstract In the presented work, the parameters of a new MAPD-3NM-II photodiode with buried pixel structure manufactured in cooperation with Zecotek Company are investigated. The photon detection efficiency, gain, capacitance and gamma-ray detection performance of photodiodes are studied. The SPECTRIG MAPD is used to measure the parameters of the MAPD-3NM-II and scintillation detector based on it. The obtained results show that the newly developed MAPD-3NM-II photodiode outperforms its counterparts in most parameters and it can be successfully applied in space application, medicine, high-energy physics and security.


Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3763 ◽  
Author(s):  
Mirko Sanzaro ◽  
Fabio Signorelli ◽  
Paolo Gattari ◽  
Alberto Tosi ◽  
Franco Zappa

Silicon photomultipliers (SiPMs) have improved significantly over the last years and now are widely employed in many different applications. However, the custom fabrication technologies exploited for commercial SiPMs do not allow the integration of any additional electronics, e.g., on-chip readout and analog (or digital) processing circuitry. In this paper, we present the design and characterization of two microelectronics-compatible SiPMs fabricated in a 0.16 µm–BCD (Bipolar-CMOS-DMOS) technology, with 0.67 mm × 0.67 mm total area, 10 × 10 square pixels and 53% fill-factor (FF). The photon detection efficiency (PDE) surpasses 33% (FF included), with a dark-count rate (DCR) of 330 kcps. Although DCR density is worse than that of state-of-the-art SiPMs, the proposed fabrication technology enables the development of cost-effective systems-on-chip (SoC) based on SiPM detectors. Furthermore, correlated noise components, i.e., afterpulsing and optical crosstalk, and photon timing response are comparable to those of best-in-class commercial SiPMs.


2014 ◽  
Vol 22 (1) ◽  
pp. 716 ◽  
Author(s):  
Seul Ki Yang ◽  
J. Lee ◽  
Sug-Whan Kim ◽  
Hye-Young Lee ◽  
Jin-A Jeon ◽  
...  

2021 ◽  
Vol 16 (4) ◽  
pp. 546-551
Author(s):  
Mei-Ling Zeng ◽  
Yang Wang ◽  
Xiang-Liang Jin ◽  
Yan Peng ◽  
Jun Luo

Single-photon avalanche diodes (SPADs) can detect extremely weak optical signals and are mostly used in single-photon imaging, quantum communication, medical detection, and other fields. In this paper, a low dark count rate (DCR) single-photon avalanche diode device is designed based on the 180 nm standard BCD process. The device has a good response in the 450~750 nm spectral range. The active area of the device adopts a P+/N-Well structure with a diameter of 20 µm. The low-doped N-Well increases the thickness of the depletion region and can effectively improve the detection sensitivity; the P-Well acts as a guard ring to prevent premature breakdown of the PN junction edge; the isolation effect of the deep N-Well reduces the noise coupling of the substrate. Use the TCAD simulation tool to verify the SPAD’s basic principles. The experimental test results show that the avalanche breakdown voltage of the device is 11.7 V. The dark count rate is only 123 Hz when the over-bias voltage is 1 V, and the peak photon detection efficiency (PDE) reaches 37.5% at the wavelength of 500 nm under the 0.5 V over-bias voltage. PDE exceeds 30% in the range of 460~640 nm spectral range, which has a good response in the blue band. The SPAD device provides certain design ideas for the research of fluorescence detectors.


2017 ◽  
Vol 31 (17) ◽  
pp. 1750193 ◽  
Author(s):  
Wei Wang ◽  
Xiaoyuan Bao ◽  
Li Chen ◽  
Ting Chen ◽  
Guanyu Wang ◽  
...  

This paper proposed a single photon avalanche diodes (SPADs) designed with 0.18 [Formula: see text] standard CMOS process. One of the major challenges in CMOS SPADs is how to raise the low photon detection efficiency (PDE). In this paper, the device structure and process parameters of the CMOS SPAD are optimized so as to improve PDE properties which have been investigated in detail. The CMOS SPADs are designed in p+/n-well/deep n-well (DNW) structure with the p-sub and the p-well guard ring (GR). The simulation results show that with the p-well GR, the quantum efficiency (QE) is about 80% with the breakdown voltage of 12.7 V, the unit responsivity is as high as 0.38 A/W and the PDE of 51% and 53% is obtained when the excess bias is at 1 V and 2 V, respectively. The dark count rate (DCR) is 6.2 kHz when bias voltage is 14 V. With the p-sub GR, the breakdown voltage is 13 V, the unit responsivity is up to 0.26 A/W, the QE is 58%, the PDE is 33% and 37% at excess bias of 1 V and 2 V, respectively. The DCR is 3.4 kHz at reverse bias voltage of 14 V.


2019 ◽  
Vol 40 (9) ◽  
pp. 1471-1474 ◽  
Author(s):  
Nicola D'Ascenzo ◽  
Emanuele Antonecchia ◽  
Andreas Brensing ◽  
Werner Brockherde ◽  
Stefan Dreiner ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document