Temperature dependences of threshold voltage and drain-induced barrier lowering in 60nm gate length MOS transistors

2014 ◽  
Vol 54 (6-7) ◽  
pp. 1109-1114 ◽  
Author(s):  
Zehua Chen ◽  
Hei Wong ◽  
Yan Han ◽  
Shurong Dong ◽  
B.L. Yang
Keyword(s):  
Threshold Voltage ◽  
Gate Length ◽  
Mos Transistors ◽  
Temperature Dependences

scholarly journals Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4092
Author(s):  
Grzegorz Blakiewicz ◽  
Jacek Jakusz ◽  
Waldemar Jendernalik
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Boost Converter ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Thermoelectric Energy ◽  
On Chip ◽  
Voltage Swing ◽  
High Output Voltage ◽  
High Output

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

Development of 8 mΩ-cm2, 1.8 kV 4H-SiC DMOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1261-1264 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Brett A. Hull ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Gate Length ◽  
Gate Bias ◽  
Low Loss ◽  
Layer Resistance ◽  
Switching Characteristics ◽  
Mos Gate ◽  
Drift Layer

8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.

Threshold voltage variations with temperature in MOS transistors

1971 ◽  
Vol 18 (6) ◽  
pp. 386-388 ◽  
Author(s):  
R. Wang ◽  
J. Dunkley ◽  
T.A. DeMassa ◽  
L.F. Jelsma
Keyword(s):  
Threshold Voltage ◽  
Mos Transistors

Threshold voltage controllability in double-diffused-MOS transistors

1974 ◽  
Vol 21 (12) ◽  
pp. 778-784 ◽  
Author(s):  
M.D. Pocha ◽  
A.G. Gonzalez ◽  
R.W. Dutton
Keyword(s):  
Threshold Voltage ◽  
Mos Transistors

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Electrical Properties of p-Channel MOSFETs Fabricated on 4H- and 6H-SiC

2007 ◽  
Vol 556-557 ◽  
pp. 783-786
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Electrical Properties ◽  
Valence Band ◽  
Threshold Voltage ◽  
Present Report ◽  
Cmos Technology ◽  
Interface State ◽  
Valence Band Edge ◽  
State Distribution ◽  
Channel Mobility ◽  
Temperature Dependences

It is of great importance to investigate the electrical properties of SiC p-channel MOSFETs for development of SiC CMOS technology. In the present report, we investigated dependences of electrical properties of the SiC p-channel MOSFETs on SiC poly-types. The on-state characteristics (channel mobility, threshold voltage, and temperature dependences) for the 4H- and 6H-SiC p-channel MOSFETs showed similar behavior, although those of 4H-SiC n-channel MOSFETs are usually quite different from those of 6H-SiC. These results might be caused by the similar SiC MOS interface state distribution around the valence band edge.

A Model of Gamma-Ray Irradiation Effects in Silicon Dioxide Films and on Silicon Dioxide - Silicon Interface

2007 ◽  
Vol 555 ◽  
pp. 147-152 ◽  
Author(s):  
M. Odalović ◽  
D. Petković
Keyword(s):  
Silicon Dioxide ◽  
Threshold Voltage ◽  
Gamma Ray ◽  
Monte Carlo Model ◽  
Mos Transistors ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Silicon Dioxide Films ◽  
Gamma Ray Irradiation ◽  
Silicon Interface

The gamma-ray irradiation causes positive charge traps formation in silicon dioxide films and at silicon dioxide - silicon interface of MOS devices, and the threshold voltage shift in MOS transistors. Here, the Monte Carlo model was used to develop an approach for estimating gammaray induced traps spatially distributed in silicon dioxide films. This is combined with the model of energy distributed traps at silicon dioxide - silicon interface. The developed model enables gammaray induced charge and threshold voltage shift determination as a function of gamma-ray doses. The threshold voltage measurements at a single specified current, both of radiation sensitive and radiation hardened MOS transistors irradiated with different doses of gamma-ray are compared with the developed model and good agreement are obtained.

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