Effects of different drop test conditions on board-level reliability of chip-scale packages

2008 ◽  
Vol 48 (2) ◽  
pp. 274-281 ◽  
Author(s):  
Yi-Shao Lai ◽  
Po-Chuan Yang ◽  
Chang-Lin Yeh
Keyword(s):  
Drop Test ◽  
Test Conditions ◽  
Board Level ◽  
Board Level Reliability

An approach to adjust the board-level drop test conditions to improve the correlation with product-level drop impact

2014 ◽  
Vol 54 (4) ◽  
pp. 785-795 ◽  
Author(s):  
T.T. Mattila ◽  
H. Ruotoistenmäki ◽  
J. Raami ◽  
J. Hokka ◽  
M. Mäkelä ◽  
...  
Keyword(s):  
Drop Impact ◽  
Drop Test ◽  
Product Level ◽  
Test Conditions ◽  
Board Level

Board Level Reliability of Automotive Grade WLCSP for Radar Applications

2020 ◽  
Author(s):  
Nishant Lakhera ◽  
Burt Carpenter ◽  
Trung Duong ◽  
Mollie Benson ◽  
Andrew J Mawer
Keyword(s):  
Radar Applications ◽  
Board Level ◽  
Board Level Reliability

Board-Level Reliability of Pb-Free Surface Mounted Assemblies during Thermal Shock Testing

2006 ◽  
Vol 15-17 ◽  
pp. 633-638 ◽  
Author(s):  
Jong Woong Kim ◽  
Hyun Suk Chun ◽  
Sang Su Ha ◽  
Jong Hyuck Chae ◽  
Jin Ho Joo ◽  
...  
Keyword(s):  
Thermal Shock ◽  
Solder Joints ◽  
Lead Frame ◽  
Shear Forces ◽  
Microstructural Investigation ◽  
Shock Testing ◽  
Ceramic Capacitor ◽  
Board Level ◽  
Board Level Reliability ◽  
Thermal Shocks

Board-level reliability of conventional Sn-37Pb and Pb-free Sn-3.0Ag-0.5Cu solder joints was evaluated using thermal shock testing. In the microstructural investigation of the solder joints, the formation of Cu6Sn5 intermetallic compound (IMC) layer was observed between both solders and Cu lead frame, but any crack or newly introduced defect cannot be found even after 2000 cycles of thermal shocks. Shear test of the multi layer ceramic capacitor (MLCC) joints were also conducted to investigate the effect of microstructural variations on the bonding strength of the solder joints. Shear forces of the both solder joints decreased with increasing thermal shock cycles. The reason to the decrease in shear force was discussed with fracture surfaces of the shear tested solder joints.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

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