Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

2004 ◽  
Vol 44 (8) ◽  
pp. 1269-1273 ◽  
Author(s):  
Guoqiao Tao ◽  
Andrea Scarpa ◽  
Leo van Marwijk ◽  
Kitty van Dijk ◽  
Fred Kuper
Keyword(s):  
Leakage Current ◽  
Memory Processes ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Stress Induced Leakage Current

Nanocrystals in High-k Dielectric Stacks for Non-Volatile Memory Applications

2006 ◽  
Vol 51 ◽  
pp. 156-166 ◽  
Author(s):  
Marco Fanciulli ◽  
Michele Perego ◽  
Caroline Bonafos ◽  
A. Mouti ◽  
S. Schamm ◽  
...  
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Research Strategies ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Materials

The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky
Keyword(s):  
Leakage Current ◽  
Electrical Performance ◽  
Constant Current ◽  
Continuous Increase ◽  
Current Stress ◽  
Thermal Oxide ◽  
Stress Induced Leakage Current ◽  
Boron Penetration ◽  
Soft Breakdown ◽  
Induced Defects

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory

Integrated low-temperature process for the fabrication of amorphous Si nanoparticles embedded in Al2 O3 for non-volatile memory application

2016 ◽  
Vol 213 (9) ◽  
pp. 2446-2451 ◽  
Author(s):  
Klemens Ilse ◽  
Thomas Schneider ◽  
Johannes Ziegler ◽  
Alexander Sprafke ◽  
Ralf B. Wehrspohn
Keyword(s):  
Low Temperature ◽  
Si Nanoparticles ◽  
Non Volatile Memory ◽  
Amorphous Si ◽  
Volatile Memory ◽  
Low Temperature Process

scholarly journals Secure Boot from Non-Volatile Memory for Programmable SoC Architectures

2020 ◽  
Author(s):  
Franz-Josef Streit ◽  
Florian Fritz ◽  
Andreas Becher ◽  
Stefan Wildermann ◽  
Stefan Werner ◽  
...  
Keyword(s):  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory

2021 ◽  
Vol 2 ◽  
pp. 31-40
Author(s):  
Jiang Li ◽  
Yijun Cui ◽  
Chongyan Gu ◽  
Chenghua Wang ◽  
Weiqiang Liu ◽  
...  
Keyword(s):  
Physical Unclonable Function ◽  
Hybrid Scheme ◽  
Non Volatile Memory ◽  
Volatile Memory

WOBTree: a write-optimized B+-tree for non-volatile memory

2021 ◽  
Vol 15 (5) ◽  
Author(s):  
Haitao Wang ◽  
Zhanhuai Li ◽  
Xiao Zhang ◽  
Xiaonan Zhao ◽  
Song Jiang
Keyword(s):  
Non Volatile Memory ◽  
Volatile Memory
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