CAEMO - A Flexible and scalable high performance matrix algebra coprocessor for embedded reconfigurable computing systems

2018 ◽  
Vol 56 ◽  
pp. 47-63
Author(s):  
Hendrik Woehrle ◽  
Frank Kirchner
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Matrix Algebra ◽  
Computing Systems ◽  
Performance Matrix

scholarly journals Reliable Generation of High-Performance Matrix Algebra

2015 ◽  
Vol 41 (3) ◽  
pp. 1-27 ◽  
Author(s):  
Thomas Nelson ◽  
Geoffrey Belter ◽  
Jeremy G. Siek ◽  
Elizabeth Jessup ◽  
Boyana Norris
Keyword(s):  
High Performance ◽  
Matrix Algebra ◽  
Performance Matrix

scholarly journals Reconfigurable Modular Computing System

2019 ◽  
Vol 23 (2) ◽  
pp. 137-152
Author(s):  
S. S. Schevelev
Keyword(s):  
Neural Networks ◽  
Pattern Recognition ◽  
Reconfigurable Computing ◽  
High Performance ◽  
Block Diagram ◽  
Computing System ◽  
Modular System ◽  
Switching Systems ◽  
Computing Systems ◽  
Logical Operations

Purpose of research. A reconfigurable computer system consists of a computing system and special-purpose computers that are used to solve the tasks of vector and matrix algebra, pattern recognition. There are distinctions between matrix and associative systems, neural networks. Matrix computing systems comprise a set of processor units connected through a switching device with multi-module memory. They are designed to solve vector, matrix and data array problems. Associative systems contain a large number of operating devices that can simultaneously process multiple data streams. Neural networks and neurocomputers have high performance when solving problems of expert systems, pattern recognition due to parallel processing of a neural network.Methods. An information graph of the computational process of a reconfigurable modular system was plotted. Structural and functional schemes, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words were developed. Software for modelling the operation of the arithmetic-symbol processor, specialized computing modules, and switching systems was developed.Results. A block diagram of a reconfigurable computing modular system was developed. The system consists of compatible functional modules and is capable of static and dynamic reconfiguration, has a parallel connection structure of the processor and computing modules through the use of interface channels. It consists of an arithmeticsymbol processor, specialized computing modules and switching systems; it performs specific tasks of symbolic information processing, arithmetic and logical operations.Conclusion. Systems with a reconfigurable structure are high-performance and highly reliable computing systems that consist of integrated processors in multi-machine and multiprocessor systems. Reconfigurability of the structure provides high system performance due to its adaptation to computational processes and the composition of the processed tasks.

Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme)

2007 ◽  
Vol 49 (3) ◽  
Author(s):  
Heiko Hinkelmann ◽  
Peter Zipf ◽  
Manfred Glesner ◽  
Thilo Pionteck
Keyword(s):  
Wireless Communication ◽  
Reconfigurable Computing ◽  
Energy Efficient ◽  
Communication Systems ◽  
High Performance ◽  
Wireless Communication Systems ◽  
Computing Systems ◽  
Dynamically Reconfigurable ◽  
Hardware Platforms ◽  
Application Specific

In this paper we will demonstrate that dynamically reconfigurable computing is the key technology to enable small and energy-efficient hardware platforms for wireless communication systems, which provide the flexibility needed for keeping up with evolving standards and protocols. Two application-specific dynamically reconfigurable systems for WLANs and wireless sensor networks will be presented. The first architecture clearly shows that highly dynamic reconfiguration approaches can provide flexible and high-performance hardware platforms that are smaller than standard ASIC solutions. The second architecture serves as a case study for the design of energy-efficient dynamically reconfigurable computing systems.

scholarly journals Self-Restoration Mechanism for Run-Time Reconfigurable Data-Stream Processors

2021 ◽  
Author(s):  
Irina Terterian
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Processing System ◽  
Maximum Level ◽  
Computing Systems ◽  
Computing Platform ◽  
Restoration Mechanism ◽  
Run Time ◽  
Computing Platforms ◽  
The Cost

The cost of a hardward failure in high-performance computing systems is usually extremely high because of the system stall where billions of operations can be lost within one second. Thus, implementation of self-restoration mechanisms is one of the most effective approaches to keep system performance on a required level. The project presents a new approach, which allows retaining the performance of the Run-Time Reconfigurable stream processing system on its maximum level. This becomes possible by development of multi-level self-restoration mechanism that consists of: restoration by FPGA-scrubbing, restoration by FPGA-slot replacement and restoration with optimum performance degradation. All above levels of restoration procedure were developed and tested on reconfigurable computing platform based on XILINX Virtex FPGA. Analysis of achieved results of the developed mechanism shows a very fast restoration of functionality and dramatic increase of lifetime of FPGA based computing platforms.

scholarly journals Self-Restoration Mechanism for Run-Time Reconfigurable Data-Stream Processors

2021 ◽  
Author(s):  
Irina Terterian
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Processing System ◽  
Maximum Level ◽  
Computing Systems ◽  
Computing Platform ◽  
Restoration Mechanism ◽  
Run Time ◽  
Computing Platforms ◽  
The Cost

The cost of a hardward failure in high-performance computing systems is usually extremely high because of the system stall where billions of operations can be lost within one second. Thus, implementation of self-restoration mechanisms is one of the most effective approaches to keep system performance on a required level. The project presents a new approach, which allows retaining the performance of the Run-Time Reconfigurable stream processing system on its maximum level. This becomes possible by development of multi-level self-restoration mechanism that consists of: restoration by FPGA-scrubbing, restoration by FPGA-slot replacement and restoration with optimum performance degradation. All above levels of restoration procedure were developed and tested on reconfigurable computing platform based on XILINX Virtex FPGA. Analysis of achieved results of the developed mechanism shows a very fast restoration of functionality and dramatic increase of lifetime of FPGA based computing platforms.

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