A low-cost, fault-tolerant and high-performance router architecture for on-chip networks

2016 ◽  
Vol 45 ◽  
pp. 151-163 ◽  
Author(s):  
Mojtaba Valinataj ◽  
Mostafa Shahiri
Keyword(s):  
High Performance ◽  
Fault Tolerant ◽  
Low Cost ◽  
Router Architecture ◽  
On Chip

scholarly journals NoCGuard: A Reliable Network-on-Chip Router Architecture

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 342 ◽  
Author(s):  
Muhammad Akmal Shafique ◽  
Naveed Khan Baloch ◽  
Muhammad Iram Baig ◽  
Fawad Hussain ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Channel Allocation ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Time To Failure ◽  
Protection Factor ◽  
Router Architecture ◽  
On Chip

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.

Designing fault-tolerant network-on-chip router architecture

2010 ◽  
Vol 97 (10) ◽  
pp. 1181-1192 ◽  
Author(s):  
Ashkan Eghbal ◽  
Pooria M. Yaghini ◽  
H. Pedram ◽  
H. R. Zarandi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Router Architecture ◽  
On Chip

Design and Calibration of MIMU Based on Chip Size Micro Inertial Sensors

2013 ◽  
Vol 849 ◽  
pp. 302-309
Author(s):  
Yun Xu ◽  
Xin Hua Zhu ◽  
Yu Wang
Keyword(s):  
High Performance ◽  
Inertial Sensors ◽  
Low Cost ◽  
Rapid Development ◽  
Experimental Result ◽  
Integrated Navigation ◽  
Bias Stability ◽  
Chip Size ◽  
Order Of Magnitude ◽  
On Chip

With rapid development of micro fabrication technology, the performance of MIMU has gradually improved. The MIMU introduced in this paper is based on the silicon micro machined gyroscope of type MSG7000D and accelerometer of type MSA6000. The volume of it is 3×3×3cm3, the mass is 68.5g and the power consumption is less than 1w. The experimental result shows that the bias stability of the gyroscope and accelerometer for each axis of the designed MIMU is less than 10°/h and 0.5mg respectively. For the non orthogonality in three axes of the structure, MIMU needs to be calibrated. After calibration, the measurement accuracy has improved by an order of magnitude. The designed MIMU can satisfy the requirement of high performance, low cost, light weight and small size for strap-down navigation system, thus it can be widely applied not only to the field of vehicles integrated navigation, attitude measurement but also to the fields of personal goods such as mobile, game consoles and so on.

scholarly journals Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

2017 ◽  
Vol E100.D (4) ◽  
pp. 910-913
Author(s):  
Ruilian XIE ◽  
Jueping CAI ◽  
Xin XIN ◽  
Bo YANG
Keyword(s):  
Fault Tolerant ◽  
Low Cost ◽  
Network On Chip ◽  
Routing Method ◽  
On Chip ◽  
2D Network

scholarly journals Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System

2018 ◽  
Vol 8 (6) ◽  
pp. 4164
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V
Keyword(s):  
Monitoring System ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Data Communication ◽  
Multiprocessor System ◽  
Packet Routing ◽  
Distributed Agents ◽  
Agent Based ◽  
On Chip

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

scholarly journals Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1783 ◽  
Author(s):  
Ayaz Hussain ◽  
Muhammad Irfan ◽  
Naveed Khan Baloch ◽  
Umar Draz ◽  
Tariq Ali ◽  
...  
Keyword(s):  
Resource Sharing ◽  
Fault Tolerant ◽  
Single Chip ◽  
Protection Factor ◽  
Technology Scaling ◽  
Router Architecture ◽  
Permanent Faults ◽  
Multiple Paths ◽  
On Chip ◽  
The Cost

The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single chip; on the other hand, it becomes the reason for faults. A generic router consists of the buffers and pipeline stages. A single fault may result in an undesirable situation of degraded performance or a whole chip may stop working. Therefore, it is necessary to provide permanent fault tolerance to all the components of the router. In this paper, we propose a mechanism that can tolerate permanent faults that occur in the router. We exploit the fault-tolerant techniques of resource sharing and paring between components for the input port unit and routing computation (RC) unit, the resource borrowing for virtual channel allocator (VA) and multiple paths for switch allocator (SA) and crossbar (XB). The experimental results and analysis show that the proposed mechanism enhances the reliability of the router architecture towards permanent faults at the cost of 29% area overhead. The proposed router architecture achieves the highest Silicon Protection Factor (SPF) metric, which is 24.8 as compared to the state-of-the-art fault-tolerant architectures. It incurs an increase in latency for SPLASH2 and PARSEC benchmark traffics, which is minimal as compared to the baseline router.

Application of WeChat Mini-Program and Wi-Fi SoC in Agricultural IoT: A Low-Cost Greenhouse Monitoring System

2020 ◽  
Vol 63 (2) ◽  
pp. 325-337
Author(s):  
Lei Zhou ◽  
Zhengjun Qiu ◽  
Yong He
Keyword(s):  
Internet Of Things ◽  
Monitoring System ◽  
High Performance ◽  
Low Cost ◽  
Rapid Development ◽  
Sensor Nodes ◽  
Sensor Data ◽  
Smart Devices ◽  
Increasing Demand ◽  
On Chip

HighlightsA quick solution for developing and deploying custom agricultural IoT systems is proposed.Low-cost and high-performance devices are used for the design of sensor nodes.A mobile application based on WeChat Mini-Program is developed for device and data management.The proposed system brings convenience to both users and developers.Abstract. Increasing demand for automatic management of agricultural production and real-time remote monitoring has increased the need for smart devices, wireless technologies, and sensors. The internet of things (IoT) has emerged as a common technology for the management of multiple devices by multiple users. Some professional solutions are relatively difficult to implement for researchers who are interested in agricultural IoT but do not have requisite skills in computers and electronics. The unfriendliness of the user software limits the practical application of agricultural IoT in China. This article presents a simple solution based on an SoC (system-on-chip) and WeChat mini-program that focuses on low-cost hardware, rapid development, user-friendly application design, and helping developers get a quick start in building a DIY monitoring system. The ESP8266, a high-performance SoC, is used as the microcontroller and Wi-Fi module to transfer the sensor data to a remote server. A WeChat mini-program provides the graphical user interface, enabling users to manage devices and access data by clicking. Users can log into the system using their WeChat accounts and bind devices by scanning QR codes on the devices. Thus, the complex management and device binding in conventional systems can be overcome. The system is easy to be expand and has great potential for greenhouse environmental monitoring in China. Keywords: Greenhouse ambient monitoring, Internet of things, WeChat mini-program, Wi-Fi SoC.

scholarly journals Low cost fault-tolerant routing algorithm for Networks-on-Chip

2015 ◽  
Vol 39 (6) ◽  
pp. 358-372 ◽  
Author(s):  
Junxiu Liu ◽  
Jim Harkin ◽  
Yuhua Li ◽  
Liam Maguire
Keyword(s):  
Fault Tolerant ◽  
Low Cost ◽  
Routing Algorithm ◽  
Networks On Chip ◽  
On Chip
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