Content addressable memory cell in quantum-dot cellular automata

2016 ◽  
Vol 163 ◽  
pp. 140-150 ◽  
Author(s):  
Saeed Rasouli Heikalabad ◽  
Ahmad Habibizad Navin ◽  
Mehdi Hosseinzadeh
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Memory Cell ◽  
Quantum Dot Cellular Automata ◽  
Content Addressable Memory

Memory Designing Using Quantum-Dot Cellular Automata: Systematic Literature Review, Classification and Current Trends

2017 ◽  
Vol 26 (12) ◽  
pp. 1730004 ◽  
Author(s):  
Sonia Afrooz ◽  
Nima Jafari Navimipour
Keyword(s):  
Cellular Automata ◽  
Literature Review ◽  
Quantum Dot ◽  
Systematic Literature Review ◽  
Random Access ◽  
Memory Cell ◽  
Memory State ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Advantages And Disadvantages

Quantum-dot cellular automata (QCA) has come out as one of the potential computational structures for the emerging nanocomputing systems. It has a large capacity in the development of circuits with high space density and dissipation of low heat and allows faster computers to develop with lower power consumption. The QCA is a new appliance to realize nanolevel digital devices and study and analyze their various parameters. It is also a potential technology for low force and high-density memory plans. Large memory designs in QCA show unique features because of their architectural structure. In QCA-based architectures, memory must be maintained in motion, i.e., the memory state has to be continuously moved through a set of QCA cells. These architectures have different features, such as the number of bits stored in a loop, access type (serial or parallel) and cell arrangement for the memory bank. However, the decisive features of the QCA memory cell design are the number of cells, to put off the use of energy. Although the review and study of the QCA-based memories are very important, there is no complete and systematic literature review about the systematical analyses of the state of the mechanisms in this field. Therefore, there are five main types to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM). Also, it has provided the advantages and disadvantages of the reviewed mechanisms and their important challenges so that some interesting lines for any coming research are provided.

DESIGN AND SIMULATION OF MODULAR QUANTUM-DOT CELLULAR AUTOMATA MULTIPLEXERS FOR MEMORY ACCESSING

2010 ◽  
Vol 19 (02) ◽  
pp. 349-365 ◽  
Author(s):  
VASILIOS A. MARDIRIS ◽  
IOANNIS G. KARAFYLLIDIS
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Modular Design ◽  
Memory Cell ◽  
Building Blocks ◽  
Careful Consideration ◽  
Quantum Dot Cellular Automata ◽  
Specific Memory ◽  
Circuit Integration ◽  
Qca Circuits

Multiplexers are extremely important parts of signal control systems. Some critical circuits of computing systems, like memories, use large multiplexers in order to present the value of a specific memory cell to their output. Several quantum-dot cellular automata (QCA) circuits have been designed and the need for a QCA memory access system becomes prominent. A modular 2n to 1 QCA multiplexer covering small area could reduce the size of such circuits and conclusively could increase circuit integration. In this paper we present a novel design of a small size, modular quantum-dot cellular automata (QCA) 2n to 1 multiplexer that can be used for memory addressing. The design objective is to develop a modular design methodology which can be used to implement 2n to 1 multiplexers using building blocks. For the QCA implementation a careful consideration is taken into account concerning the design in order to increase the circuit stability.

Designing High Speed Sequential Circuits by Quantum-Dot Cellular Automata: Memory Cell and Counter Study

2015 ◽  
Vol 4 (2) ◽  
pp. 190-197 ◽  
Author(s):  
Shadi Sheikhfaal ◽  
Keivan Navi ◽  
Shaahin Angizi ◽  
Ahmad Habibizad Navin
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Memory Cell ◽  
Sequential Circuits ◽  
Quantum Dot Cellular Automata

TCAM/CAM-QCA: (Ternary) Content Addressable Memory using Quantum-dot Cellular Automata

2015 ◽  
Vol 46 (7) ◽  
pp. 563-571 ◽  
Author(s):  
Luiz H.B. Sardinha ◽  
Douglas S. Silva ◽  
Marcos A.M. Vieira ◽  
Luiz F.M. Vieira ◽  
Omar P. Vilela Neto
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory

scholarly journals Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

2021 ◽  
Vol 3 (10) ◽  
Author(s):  
Mohammad Enayati ◽  
Abdalhossein Rezai ◽  
Asghar Karimi
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Network Routing ◽  
Memory Unit ◽  
Quantum Dot Cellular Automata ◽  
Content Addressable Memory ◽  
Computational Circuits ◽  
Short Time ◽  
Fast Memory ◽  
Number Of Cells

AbstractQuantum-dot cellular automata (QCA) technology is a kind of nanotechnology utilized for building computational circuits. It can be a good technology for overcome CMOS drawbacks at nano-scale due to its low delay and area. The Content-Addressable Memory (CAM) is a very fast memory that can perform search operations in a very short time. This feature makes the relative popularity of these memories and many applications for them, especially in network routing and processors. In this study, a novel loop-based circuit is designed for the QCA memory unit, which reduces area, cell count, latency, and cost. The obtained results using QCADesigner tool version 2.0.3 demonstrate that the designed QCA memory unit utilizes 16 cells, 0.01 µm2 area, and 0.25 clock cycles and has a reduction of 33% in the number of cells, 50% in area, 50% in latency, and 75% in cost compared to existing works. Then, this memory unit is utilized to design an efficient structure for CAM circuit. The results show that the developed structure for CAM circuit has 0.75 clock cycles, 32 cells, and 0.03 µm2 area, and it has a reduction of 20% in the number of cells, 25% in area, 40% in latency, and 75% in cost compared to existing works.

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