Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking

2016 ◽  
Vol 156 ◽  
pp. 24-29 ◽  
Author(s):  
Chang-Chun Lee ◽  
Yu-Min Lin ◽  
Chia-Ping Hsieh ◽  
Yan-Yu Liou ◽  
Chau-Jie Zhan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Technology Development ◽  
Three Dimensional ◽  
Circuit Integration ◽  
Assembly Technology ◽  
Three Dimensional Integrated Circuit

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

2014 ◽  
Vol 136 (4) ◽  
Author(s):  
John H. Lau
Keyword(s):  
Integrated Circuit ◽  
State Of The Art ◽  
Three Dimensional ◽  
High Volume ◽  
3D Integration ◽  
3D Ic ◽  
3D Ic Packaging ◽  
Ic Packaging ◽  
Circuit Integration ◽  
Three Dimensional Integrated Circuit

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

Gold and palladium embrittlement issues in three-dimensional integrated circuit interconnections

2013 ◽  
Vol 110 ◽  
pp. 13-15 ◽  
Author(s):  
Y.J. Chen ◽  
T.L. Yang ◽  
J.J. Yu ◽  
C.L. Kao ◽  
C.R. Kao
Keyword(s):  
Integrated Circuit ◽  
Three Dimensional ◽  
Three Dimensional Integrated Circuit
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