scholarly journals Conversion of Mersenne Twister to double-precision floating-point numbers

2019 ◽  
Vol 161 ◽  
pp. 76-83 ◽  
Author(s):  
Shin Harase
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Mersenne Twister ◽  
Floating Point Numbers

scholarly journals On fixpoints of Higham’s function

2021 ◽  
Vol 37 (2) ◽  
pp. 355-360
Author(s):  
RADU T. TRÎMBIŢAŞ
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Square Roots ◽  
Floating Point Arithmetic ◽  
Ieee Standard ◽  
Point Arithmetic ◽  
Floating Point Numbers

We study the strange behavior in floating-point arithmetic of a function proposed by Nicholas Higham, consisting of repeated square roots extraction followed by the same number of times squaring and find its fixpoints. For IEEE standard double precision floating point numbers the fixpoints have the form \[ x \in \left\{\left( 1+k\mathrm{eps}\right) ^{\frac{1}{\mathrm{eps}}},\quad k=\left[ -745:\frac{1}{2}:-\frac{1}{2},0:709\right]\right\} \cup \{0\} , \] where \mathrm{eps} is the machine epsilon."

scholarly journals Scaling Up and Down of 3-D Floating-point Data in Quantum Computation

2021 ◽  
Author(s):  
Meiyu Xu ◽  
Dayong Lu ◽  
Xiaoyun Sun
Keyword(s):  
Quantum Computation ◽  
Scaling Up ◽  
Floating Point ◽  
Geometric Transformation ◽  
Double Precision ◽  
Quantum Image ◽  
Image Scaling ◽  
Trilinear Interpolation ◽  
Point Data ◽  
Floating Point Numbers

Abstract In the past few decades, quantum computation has become increasingly attractivedue to its remarkable performance. Quantum image scaling is considered a common geometric transformation in quantum image processing, however, the quantum floating-point data version of which does not exist. Is there a corresponding scaling for 2-D and 3-D floating-point data? The answer is yes.In this paper, we present quantum scaling up and down scheme for floating-point data by using trilinear interpolation method in 3-D space. This scheme offers better performance (in terms of the precision of floating-point numbers) for realizing the quantum floating-point algorithms compared to previously classical approaches. The Converter module we proposed can solve the conversion of fixed-point numbers to floating-point numbers of arbitrary size data with p + q qubits based on IEEE-754 format, instead of 32-bit single-precision, 64-bit double precision or 128-bit extended-precision. Usually, we use nearest neighbor interpolation and bilinear interpolation to achieve quantum image scaling algorithms, which are not applicable in high-dimensional space. This paper proposes trilinear interpolation of floating-point numbers in 3-D space to achieve quantum algorithms of scaling up and down for 3-D floating-point data. Finally, the circuits of quantum scaling up and down for 3-D floating-point data are designed.

scholarly journals A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 165740-165747
Author(s):  
Juwon Yun ◽  
Jinyoung Lee ◽  
Woo-Nam Chung ◽  
Cheong Ghil Kim ◽  
Woo-Chan Park
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Floating Point Numbers

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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