Making-a-stop: A new bufferless routing algorithm for on-chip network

2012 ◽  
Vol 72 (4) ◽  
pp. 515-524 ◽  
Author(s):  
Jing Lin ◽  
Xiaola Lin ◽  
Liang Tang
Keyword(s):  
Routing Algorithm ◽  
On Chip

scholarly journals Load-balanced routing algorithm for Network-on-Chip employing fair arbiter

2021 ◽  
Vol 1871 (1) ◽  
pp. 012117
Author(s):  
Lu Liu ◽  
Yanfei Yang ◽  
Qianqian Lei ◽  
Huhu Wang ◽  
Song Lixun
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
On Chip ◽  
Load Balanced

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

A congestion-aware routing algorithm for mesh-based platform networks-on-chip

2021 ◽  
pp. 105145
Author(s):  
N. Taherkhani ◽  
R. Akbar ◽  
F. Safaei ◽  
M. Moudi
Keyword(s):  
Routing Algorithm ◽  
Networks On Chip ◽  
On Chip ◽  
Congestion Aware

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Level Based Routing Using Dynamic Programming for 2D Mesh

2017 ◽  
Vol 17 (2) ◽  
pp. 73-82 ◽  
Author(s):  
Akash Punhani ◽  
Pardeep Kumar ◽  
Nitin Nitin
Keyword(s):  
Dynamic Programming ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Networks On Chip ◽  
Mesh Topology ◽  
On Chip

Abstract The performance of the interconnection network doesn’t only depend on the topology, but it also depends on the Routing algorithm used. The simplest Routing algorithm for the mesh topology in networks on chip is the XY Routing algorithm. The level based Routing algorithm has been proved to be more efficient than the XY Routing algorithm. In this paper, level based Routing algorithm using the dynamic programming has been proposed. The proposed Routing algorithm proves to be more efficient in the terms of the computation. The proposed Routing algorithm has achieved up to two times bigger speed.

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