Numerical simulation of conventional capillary flow and no-flow underfill in flip-chip packaging

2008 ◽  
Vol 37 (5) ◽  
pp. 520-523 ◽  
Author(s):  
Tomohisa Hashimoto ◽  
Tanifuji Shin-ichiro ◽  
Koji Morinishi ◽  
Nobuyuki Satofuka
Keyword(s):  
Numerical Simulation ◽  
Flip Chip ◽  
Capillary Flow ◽  
Flip Chip Packaging

Underflow Process for Direct-Chip-Attachment Packaging

1998 ◽  
Vol 515 ◽  
Author(s):  
P. C. Li ◽  
G. L. Lehmann ◽  
J. Cascio ◽  
T. Driscoll ◽  
Y. J. Huang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Capillary Flow ◽  
Flow Behavior ◽  
Complex Function ◽  
Plane Channel ◽  
Flow Process ◽  
Wetting Properties ◽  
Solder Bumps ◽  
Flip Chip Packaging ◽  
Measured Flow

ABSTRACTIn flip-chip packaging an underfill mixture is placed into the chip-to-substrate standoff created by the array of solder bumps, using a capillary flow process. The flow behavior is a complex function of the mixture properties, the wetting properties, and the flow geometry. This paper reports on the use of a plane channel capillary flow to characterize underfill materials. The measured flow behavior provides evidence that both the contact angle (θ) and the suspension viscosity (μapp) vary with time under the Influence of changing flow conditions. This nonlinear fluid behavior is modeled for the flow of both model suspensions and commercial underfill materials using an extended Washburn model.

Numerical Simulation of Underfill Flow in Flip-Chip Packaging

2009 ◽  
pp. 573-578
Author(s):  
Tomohisa Hashimoto ◽  
Keiichi Saito ◽  
Koji Morinishi ◽  
Nobuyuki Satofuka
Keyword(s):  
Numerical Simulation ◽  
Flip Chip ◽  
Underfill Flow ◽  
Flip Chip Packaging

Effect of Warpage of Flip Chip Packages Due to the Underfill Encapsulating Process on Interconnect Reliability

2009 ◽  
Vol 131 (3) ◽  
Author(s):  
Satoru Katsurayama ◽  
Hironori Tohmyoh
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Capillary Flow ◽  
Curing Process ◽  
Assembly Process ◽  
Test Circuit ◽  
Interconnect Reliability ◽  
Flip Chip Packaging ◽  
Underfill Material

In flip chip packages, it is common practice for interconnects to be encapsulated with a liquid underfill material. This paper describes the effects of different underfill processes, i.e., the conventional capillary-flow underfill and two no-flow underfill processes, on flip chip packaging. The warpage of the package was examined, and the value of this during three different underfill encapsulating processes was measured. In addition, the interconnect reliability of the bump bonds after thermal-cycling was evaluated using a test circuit. The warpage of the package before curing varied depending on the assembly process, but that after curing was almost the same for all the processes studied. It was found that the interconnect reliability is closely related to the differences in the warpage arising from the assembly process, and that the smaller change in warpage introduced by the curing process gave a higher interconnect reliability for the bump bonds. Based on these findings, lower curing temperatures are considered to be more effective for improving the mountability of the package and the interconnect reliability.

A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

2014 ◽  
Vol 62 (10) ◽  
pp. 2337-2356 ◽  
Author(s):  
Bon-Hyun Ku ◽  
Ozgur Inac ◽  
Michael Chang ◽  
Hyun-Ho Yang ◽  
Gabriel M. Rebeiz
Keyword(s):  
Flip Chip ◽  
Phased Array ◽  
High Isolation ◽  
High Linearity ◽  
Flip Chip Packaging

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Process Time ◽  
Curing Process ◽  
Curing Time ◽  
Hold Temperature ◽  
Flip Chip Packaging ◽  
Time Cycle ◽  
The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

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