Performance optimization with propagation delay analysis in WDM networks

2007 ◽  
Vol 30 (18) ◽  
pp. 3572-3585 ◽  
Author(s):  
P.A. Baziana ◽  
I.E. Pountourakis
Keyword(s):  
Performance Optimization ◽  
Propagation Delay ◽  
Wdm Networks ◽  
Delay Analysis

scholarly journals An Optimized CB-UT Multiplier for Efficient Design of the AM Operator

2020 ◽  
Author(s):  
Hari Krishna Modalavalasa
Keyword(s):  
Signal Processing ◽  
Performance Optimization ◽  
High Speed ◽  
High Performance ◽  
New Technology ◽  
Digital Signal ◽  
Propagation Delay ◽  
Efficient Design ◽  
Silicon Area ◽  
Low Area

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In today's technology, Add-Multiply (AM) operator or Multiply Accumulator (MAC) units are generally employed in all high performance digital signal processors (DSP) and controllers. The performance of AM operator mainly depends on the speed of multiplier. A lot of research has been contributed in this area and the conventional multipliers were modified to provide good speed performance but needs to be improved further along with area optimization. Urdhwa-Tiryakbhyam Multiplier (UTM) architecture is adopted from ancient Indian mathematics "Vedas’ and can generate the partial products and sums in one step, which reduces the carry propagation from LSB to MSB. UTM can be used to implement high performance AM operators but results in larger silicon areas. This increased area can be minimized by using the modified compressor based design of UTM. In this work, the carrylook-ahead (CLA) adder is adopted instead of parallel adders for high speed of accumulation. So, the Compressor-Based-Urdhwa-Tiryakbhyam (CB-UT) multiplier with CLA results in both area and performance optimization of Add-Multiply operator. The functionality of this architecture is evaluated by comparing with the Modified Booth (MB) multiplier based AM operator in terms of performance parameters like propagation delay, power consumption and silicon-area. The design is implemented and verified using Xilinx Spartan-3E FPGA and ISE Simulator.

scholarly journals Propagation Delay Analysis of a Soft Open Defect inside a TSV

2011 ◽  
Vol 4 (1) ◽  
pp. 119-126 ◽  
Author(s):  
Shohei Kondo ◽  
Hiroyuki Yotsuyanagi ◽  
Masaki Hashizume
Keyword(s):  
Propagation Delay ◽  
Delay Analysis ◽  
Open Defect

Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects

2013 ◽  
Vol 13 (1) ◽  
pp. 300-306 ◽  
Author(s):  
Devendra Kumar Sharma ◽  
Brajesh Kumar Kaushik ◽  
R. K. Sharma
Keyword(s):  
Signal Integrity ◽  
Propagation Delay ◽  
Delay Analysis ◽  
Vlsi Interconnects
Sign in / Sign up

Export Citation Format

Share Document