Measurement of non-DLVO force on a silicon substrate coated with ammonium poly(acrylic acid) using scanning probe microscopy

2009 ◽  
Vol 255 (20) ◽  
pp. 8710-8713 ◽  
Author(s):  
Toshihiro Isobe ◽  
Yosuke Nakano ◽  
Yoshikazu Kameshima ◽  
Akira Nakajima ◽  
Kiyoshi Okada
2005 ◽  
Vol 862 ◽  
Author(s):  
J. M. Son ◽  
J. M. Kim ◽  
Y. Khang ◽  
E. H. Lee ◽  
S. I. Park ◽  
...  

AbstractScanning probe microscopy (SPM) with a conducting tip has been used to electrically probe silicon nanocrystals (NCs) on an insulating substrate. NC samples were produced by aerosol techniques followed by a sharpening oxidation. The size of NCs is in the range of 10-50nm and deposited on a silicon substrate with a density of around 1011/cm2. Using a conducting tip, the charge was injected directly into the NCs, and the bias dependent images due to the trapped charges in the NCs were monitored. Charging effects affected by the size of NCs and injection direction were also estimated from the apparent height differences of the NCs with respect to the applied bias.


Author(s):  
Kevin M. Shakesheff ◽  
Martyn C. Davies ◽  
Clive J. Roberts ◽  
Saul J. B. Tendler ◽  
Philip M. Williams

Author(s):  
Benedict Drevniok ◽  
St. John Dixon-Warren ◽  
Oskar Amster ◽  
Stuart L Friedman ◽  
Yongliang Yang

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.


Author(s):  
Swaminathan Subramanian ◽  
Khiem Ly ◽  
Tony Chrastecky

Abstract Visualization of dopant related anomalies in integrated circuits is extremely challenging. Cleaving of the die may not be possible in practical failure analysis situations that require extensive electrical fault isolation, where the failing die can be submitted of scanning probe microscopy analysis in various states such as partially depackaged die, backside thinned die, and so on. In advanced technologies, the circuit orientation in the wafer may not align with preferred crystallographic direction for cleaving the silicon or other substrates. In order to overcome these issues, a focused ion beam lift-out based approach for site-specific cross-section sample preparation is developed in this work. A directional mechanical polishing procedure to produce smooth damage-free surface for junction profiling is also implemented. Two failure analysis applications of the sample preparation method to visualize junction anomalies using scanning microwave microscopy are also discussed.


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