Si layer transfer to InP substrate using low-temperature wafer bonding

2006 ◽  
Vol 253 (3) ◽  
pp. 1243-1246 ◽  
Author(s):  
J. Arokiaraj ◽  
S. Tripathy ◽  
S. Vicknesh ◽  
S.J. Chua
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Layer Transfer ◽  
Inp Substrate

Strained-Si-on-Insulator (SSOI) and SiGe-on-Insulator (SGOI): Fabrication Obstacles and Solutions

2002 ◽  
Vol 745 ◽  
Author(s):  
Gianni Taraschi ◽  
Arthur J. Pitera ◽  
Lisa M. McGill ◽  
Zhi-Yuan Cheng ◽  
Minjoo L. Lee ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Material Removal ◽  
High Mobility ◽  
Layer Transfer ◽  
Strained Si ◽  
Precise Control ◽  
Bonding Structure ◽  
Selective Etch ◽  
Final Layer

ABSTRACTAdvanced CMOS substrates composed of ultra-thin strained-Si and SiGe-on-insulator were fabricated, combining both the benefits of high-mobility strained-Si and SOI. Our pioneering method employed wafer bonding of SiGe virtual substrates (with strained-Si layers) to oxidized handle wafers. Layer transfer onto insulating handle wafers can be accomplished using grind-etchback or delamination via implantation. Both methods were found to produce a rough transferred layer, but polishing is unacceptable due to non-uniform material removal across the wafer and the lack of precise control over the final layer thickness. To solve these problems, a strained-Si stop layer was incorporated into the bonding structure. After layer transfer, excess SiGe was removed using a selective etch process, stopping on the strained-Si. Within the context of ultra-thin SSOI and SGOI fabrication, this paper describes recent improvements including metastable stop layers, low temperature wafer bonding, and improved selective SiGe removal.

Low temperature InP layer transfer onto Si by helium implantation and direct wafer bonding

2006 ◽  
Vol 21 (9) ◽  
pp. 1311-1314 ◽  
Author(s):  
R Singh ◽  
I Radu ◽  
R Scholz ◽  
C Himcinschi ◽  
U Gösele ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Layer Transfer ◽  
Direct Wafer Bonding ◽  
Helium Implantation

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Low temperature GaAs/Si direct wafer bonding

2000 ◽  
Vol 36 (7) ◽  
pp. 677 ◽  
Author(s):  
M. Alexe ◽  
V. Dragoi ◽  
M. Reiche ◽  
U. Gösele
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Direct Wafer Bonding ◽  
Low Temperature Gaas

High performance InAs quantum dot lasers on silicon substrates by low temperature Pd-GaAs wafer bonding

2015 ◽  
Vol 107 (26) ◽  
pp. 261107 ◽  
Author(s):  
Zihao Wang ◽  
Ruizhe Yao ◽  
Stefan F. Preble ◽  
Chi-Sen Lee ◽  
Luke F. Lester ◽  
...  
Keyword(s):  
Low Temperature ◽  
Quantum Dot ◽  
Wafer Bonding ◽  
High Performance ◽  
Silicon Substrates ◽  
Quantum Dot Lasers ◽  
Gaas Wafer ◽  
Inas Quantum Dot
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