very-large-scale integrated circuit

2011 ◽  
Keyword(s):  
Integrated Circuit ◽  
Large Scale

scholarly journals A Review on Terahertz Technologies Accelerated by Silicon Photonics

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1646
Author(s):  
Jingya Xie ◽  
Wangcheng Ye ◽  
Linjie Zhou ◽  
Xuguang Guo ◽  
Xiaofei Zang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Silicon Photonics ◽  
Large Scale ◽  
Cost Effective ◽  
Single Chip ◽  
Photonic Integrated Circuit ◽  
Hybrid Silicon ◽  
The Cost ◽  
Silicon Based ◽  
Thz Applications

In the last couple of decades, terahertz (THz) technologies, which lie in the frequency gap between the infrared and microwaves, have been greatly enhanced and investigated due to possible opportunities in a plethora of THz applications, such as imaging, security, and wireless communications. Photonics has led the way to the generation, modulation, and detection of THz waves such as the photomixing technique. In tandem with these investigations, researchers have been exploring ways to use silicon photonics technologies for THz applications to leverage the cost-effective large-scale fabrication and integration opportunities that it would enable. Although silicon photonics has enabled the implementation of a large number of optical components for practical use, for THz integrated systems, we still face several challenges associated with high-quality hybrid silicon lasers, conversion efficiency, device integration, and fabrication. This paper provides an overview of recent progress in THz technologies based on silicon photonics or hybrid silicon photonics, including THz generation, detection, phase modulation, intensity modulation, and passive components. As silicon-based electronic and photonic circuits are further approaching THz frequencies, one single chip with electronics, photonics, and THz functions seems inevitable, resulting in the ultimate dream of a THz electronic–photonic integrated circuit.

Large scale integrated circuit chip for an electronic organ

1981 ◽  
Vol 69 (1) ◽  
pp. 338-338
Author(s):  
Harold O. Schwartz ◽  
Dennis E. Kidd
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Electronic Organ

scholarly journals Vlsi Interconnection Modelling Using a Finite Element Approach

1995 ◽  
Vol 18 (3) ◽  
pp. 179-202
Author(s):  
Umesh Kumar
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Low Complexity ◽  
Stratified Medium ◽  
Base Function ◽  
Large Scale Integration ◽  
Element Approach ◽  
Scale Integration ◽  
High Degree ◽  
Important Shift

In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.

scholarly journals Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

2020 ◽  
Vol 9 (3) ◽  
pp. 3510-3516
Keyword(s):  
Image Compression ◽  
Compression Ratio ◽  
Integrated Circuit ◽  
Large Scale ◽  
Image Data ◽  
High Compression Ratio ◽  
Compression Technique ◽  
Research Challenges ◽  
High Compression ◽  
Image Pixels

The domain of image signal processing, image compression is the significant technique, which is mainly invented to reduce the redundancy of image data in order to able to transmit the image pixels with high quality resolution. The standard image compression techniques like losseless and lossy compression technique generates high compression ratio image with efficient storage and transmission requirement respectively. There are many image compression technique are available for example JPEG, DWT and DCT based compression algorithms which provides effective results in terms of high compression ratio with clear quality image transformation. But they have more computational complexities in terms of processing, encoding, energy consumption and hardware design. Thus, bringing out these challenges, the proposed paper considers the most prominent research papers and discuses FPGA architecture design and future scope in the state of art of image compression technique. The primary aim to investigate the research challenges toward VLSI designing and image compression. The core section of the proposed study includes three folds viz standard architecture designs, related work and open research challenges in the domain of image compression.

Conversion Method of Description Files in Structural Testing of Digital Circuit

2013 ◽  
Vol 427-429 ◽  
pp. 1285-1288
Author(s):  
Kang Yi Wang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Structural Testing ◽  
Digital Logic ◽  
Continuous Development ◽  
Program Correctness ◽  
Testing Program ◽  
Circuit Technology

With the continuous development of large-scale integrated circuit technology, the importance of structural testing and testability design for digital logic circuit has become increasingly evident. In the testing domain, Bench is the most commonly used formats to describe a measured circuit. In order to test the measured circuit using computer, files with various formats must be converted to a netlist file which can be identified by computer. Lev format is a common netlist file. This paper mainly discusses how to convert the Bench file into Lev file, and it is proved by testing program correctness and robustness.

ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis

2018 ◽  
Vol 30 (9) ◽  
pp. 2472-2499 ◽  
Author(s):  
Zhitong Qiao ◽  
Yan Han ◽  
Xiaoxia Han ◽  
Han Xu ◽  
Will X. Y. Li ◽  
...  
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Large Scale ◽  
Random Number Generator ◽  
Core Area ◽  
Dynamical Model ◽  
Volterra Model ◽  
Nonlinear Dynamical ◽  
The Core ◽  
Nonlinear Dynamical Model

A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)–generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm[Formula: see text] and test power of 84.4 [Formula: see text]W. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.

Sign in / Sign up

Export Citation Format

Share Document