Pre-Silicon Verification Using Multi-FPGA Platforms: A Review

Silicon verification of flare model & application to real chip for long range proximity correction

10.1117/12.714352 ◽

2007 ◽

Author(s):

Dongqing Zhang ◽

Byoung Il Choi ◽

Foong Yee Mei ◽

Suleni T. Mulia ◽

Jung Yu Hsieh ◽

...

Keyword(s):

Long Range ◽

Model Application ◽

Silicon Verification ◽

Flare Model

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Silicon Verification using High-Level Design Tools (Abstract Only)

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '15 ◽

10.1145/2684746.2689131 ◽

2015 ◽

Cited By ~ 1

Author(s):

Tomasz S. Czajkowski

Keyword(s):

Design Tools ◽

Level Design ◽

High Level ◽

Silicon Verification

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Post-silicon verification for cache coherence

2008 IEEE International Conference on Computer Design ◽

10.1109/iccd.2008.4751884 ◽

2008 ◽

Cited By ~ 20

Author(s):

Andrew DeOrio ◽

Adam Bauserman ◽

Valeria Bertacco

Keyword(s):

Cache Coherence ◽

Silicon Verification

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Evolutionary Computation in pre-silicon verification of complex microprocessors

2009 IEEE Workshop on Evolvable and Adaptive Hardware ◽

10.1109/weah.2009.4925664 ◽

2009 ◽

Author(s):

Burcin Aktan ◽

Garrison W. Greenwood

Keyword(s):

Evolutionary Computation ◽

Silicon Verification

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Using embedded infrastructure IP for SOC post-silicon verification

10.1109/dac.2003.1219103 ◽

2004 ◽

Author(s):

Yu Huang ◽

Wu-Tung Cheng

Keyword(s):

Silicon Verification

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Mismatch circuit aging modeling and simulations for robust product design and pre-/post-silicon verification

2016 IEEE International Reliability Physics Symposium (IRPS) ◽

10.1109/irps.2016.7574591 ◽

2016 ◽

Author(s):

Hyewon Shim ◽

Yoohwan Kim ◽

Jongwook Jeon ◽

Yongsang Cho ◽

Jongwoo Park ◽

...

Keyword(s):

Product Design ◽

Modeling And Simulations ◽

Circuit Aging ◽

Silicon Verification ◽

Robust Product Design

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Addressing the systems-in-silicon verification challenge: a new approach to logic verification

Proceedings. IEEE International Verilog HDL Conference ◽

10.1109/ivc.1996.496024 ◽

2002 ◽

Author(s):

S. Caplow ◽

M. Sottak ◽

D. Kelf

Keyword(s):

New Approach ◽

Logic Verification ◽

Silicon Verification

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Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

Proceedings of the 48th Design Automation Conference on - DAC '11 ◽

10.1145/2024724.2024856 ◽

2011 ◽

Cited By ~ 14

Author(s):

Allon Adir ◽

Amir Nahir ◽

Gil Shurek ◽

Avi Ziv ◽

Charles Meissner ◽

...

Keyword(s):

Silicon Verification

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The double-sign anomaly of the Hall coefficient in amorphous silicon: Verification by computer simulations

Philosophical Magazine Letters ◽

10.1080/09500839208207540 ◽

1992 ◽

Vol 65 (5) ◽

pp. 225-231 ◽

Cited By ~ 11

Author(s):

J. M. Holender ◽

G. J. Morgan

Keyword(s):

Amorphous Silicon ◽

Computer Simulations ◽

Hall Coefficient ◽

Silicon Verification

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An Integrated on-Silicon Verification Method for FPGA Overlays

Journal of Electronic Testing ◽

10.1007/s10836-019-05786-z ◽

2019 ◽

Vol 35 (2) ◽

pp. 173-189 ◽

Cited By ~ 3

Author(s):

Alexandra Kourfali ◽

Florian Fricke ◽

Michael Huebner ◽

Dirk Stroobandt

Keyword(s):

Verification Method ◽

Silicon Verification

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