On the analysis of exit-channel effects in three-atom unimolecular reactions

1998 ◽  
Vol 4 (2) ◽  
pp. 169-179 ◽  
Author(s):  
L. Bonnet ◽  
J.C. Rayez
Keyword(s):  
Exit Channel ◽  
Unimolecular Reactions ◽  
Channel Effects

Entrance- and Exit-Channel Effects and the Suppression of Neutron Emission fromNi64+Zr92→Er*156

1986 ◽  
Vol 57 (5) ◽  
pp. 551-554 ◽  
Author(s):  
D. J. G. Love ◽  
P. J. Bishop ◽  
A. Kirwan ◽  
P. J. Nolan ◽  
D. J. Thornley ◽  
...  
Keyword(s):  
Neutron Emission ◽  
Exit Channel ◽  
Channel Effects

Exit channel effects in the reaction 19(p, α)16O

1977 ◽  
Vol 275 (2) ◽  
pp. 269-279 ◽  
Author(s):  
A. Stäbler ◽  
W. Buck ◽  
G. Staudt ◽  
H. Oeschler
Keyword(s):  
Exit Channel ◽  
Channel Effects

Comment on ‘‘Entrance- and exit-channel effects and the suppression of neutron emission fromNi64+92Zr→156Er’’

1987 ◽  
Vol 58 (15) ◽  
pp. 1584-1584 ◽  
Author(s):  
A. Ruckelshausen ◽  
B. Haas ◽  
D. Habs ◽  
R. V. F. Janssens ◽  
T. L. Khoo ◽  
...  
Keyword(s):  
Neutron Emission ◽  
Exit Channel ◽  
Channel Effects

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Study ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Gate

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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