An optimal channel-routing algorithm for a restricted class of multi-terminal nets

1991 ◽  
pp. 322-328
Author(s):  
Dee Parks
Keyword(s):  
Routing Algorithm ◽  
Restricted Class ◽  
Channel Routing

scholarly journals An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽  
1994 ◽  
Vol 1 (3) ◽  
pp. 233-242 ◽  
Author(s):  
Xiaoyu Song
Keyword(s):  
Routing Algorithm ◽  
Difficult Problem ◽  
Layout Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Vlsi Layout ◽  
Channel Density ◽  
Optimum Algorithm ◽  
Important Time ◽  
Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

scholarly journals Reducing the Delay by Optimizing the Via in Compact Automatic Metal Routing Algorithm

2019 ◽  
Vol 8 (10) ◽  
pp. 4512-4515
Keyword(s):  
Routing Algorithm ◽  
Deep Submicron ◽  
Clock Tree ◽  
Channel Routing ◽  
Ir Drop ◽  
Clock Tree Synthesis ◽  
Tree Synthesis ◽  
Metal Layers ◽  
Synthesis Stage

The Very Deep Submicron Technology (VDSM) shrinking rapidly, we have 22nm, 14nm, 7nm and now research going on 5nm technology. That means size of the transistor shrinking, and number of interconnections increased as well. Resulting interconnections playing a major role in delay, IR drop, area etc. To reduce the delay, we are utilizing higher metal layers. Further we gone for Compact Automatic Metal Routing, nothing but Over the cell channel routing to efficiently perform routing, but the problem for such type of routing technique, stacked vias needed and that results increased resistance, delay, IR drop will degrade the performance. That may be obstacle to meet timing in Clock Tree Synthesis stage (CTS). This paper mainly focus on reducing the delay further by designing the via structure by using the tool cadence encounter

A simulated annealing channel routing algorithm

CALCOLO ◽  
1990 ◽  
Vol 27 (3-4) ◽  
pp. 279-290
Author(s):  
A. Rossi
Keyword(s):  
Simulated Annealing ◽  
Routing Algorithm ◽  
Channel Routing

INTEGRATED CIRCUIT CHANNEL ROUTING USING A PARETO-OPTIMAL GENETIC ALGORITHM

2012 ◽  
Vol 21 (05) ◽  
pp. 1250041
Author(s):  
THEODORE W. MANIKAS
Keyword(s):  
Integrated Circuit ◽  
Routing Algorithm ◽  
Signal Propagation ◽  
Pareto Optimal ◽  
Signal Delay ◽  
Integrated Circuit Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Propagation Delays ◽  
Optimal Approach

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

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