An array partitioning analysis for parallel loop distribution

Author(s):  
Marc Le Fur ◽  
Jean-Louis Pazat ◽  
Françoise André
Keyword(s):  
Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 279 ◽  
Author(s):  
J. Coballes-Pantoja ◽  
R. Gómez-Fuentes ◽  
J. R. Noriega ◽  
L. A. García-Delgado

This paper is focused in the development of a parallel control loop of the angular velocity and torque for Brushless Direct Current (BLDC) motors. This parallel loop is proposed as an improvement for the performance of those cascaded solutions commonly reported in the body of literature of the field. Performance is improved by reducing the steady state error of the speed considerably when compared with the typical cascaded loop solution under a commanded change of torque. In addition, the steady state response of the parallel loop is reached in a shorter time. Simulations were designed to carry out a comparison between both methodologies. The results of these simulations consider only changes in the set point for speed or torque and are reported here. The control signal was applied to a simulated driver using a switching method known as Direct Torque Control of 2 and 3 phases (DTC-2+3P). These preliminary results show that the parallel control loop outperforms the cascaded control of BLDC motors.


1997 ◽  
Vol 5 (1) ◽  
pp. 26-40
Author(s):  
S.F. Hummel ◽  
D. Kimelman ◽  
E. Schonberg ◽  
M. Tennenhouse ◽  
D. Zernik

2011 ◽  
Vol 22 (9) ◽  
pp. 2222-2234 ◽  
Author(s):  
Gui-Bin WANG ◽  
Xue-Jun YANG ◽  
Xin-Hai XU ◽  
Yi-Song LIN ◽  
Xin LI

2022 ◽  
Vol 27 (3) ◽  
pp. 1-23
Author(s):  
Mari-Liis Oldja ◽  
Jangryul Kim ◽  
Dowhan Jeong ◽  
Soonhoi Ha

Although dataflow models are known to thrive at exploiting task-level parallelism of an application, it is difficult to exploit the parallelism of data, represented well with loop structures, since these structures are not explicitly specified in existing dataflow models. SDF/L model overcomes this shortcoming by specifying the loop structures explicitly in a hierarchical fashion. We introduce a scheduling technique of an application represented by the SDF/L model onto heterogeneous processors. In the proposed method, we explore the mapping of tasks using an evolutionary meta-heuristic and schedule hierarchically in a bottom-up fashion, creating parallel loop schedules at lower levels first and then re-using them when constructing the schedule at a higher level. The efficiency of the proposed scheduling methodology is verified with benchmark examples and randomly generated SDF/L graphs.


2002 ◽  
Vol 2002 (0) ◽  
pp. 217-218
Author(s):  
Hideaki WATANABE ◽  
Fumito KAMINAGA ◽  
Kunihito MATSUMURA

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