scholarly journals Electrical characterization of low temperature deposited oxide films on ZnO/n-Si substrate

2003 ◽  
Vol 26 (7) ◽  
pp. 693-697 ◽  
Author(s):  
S. K. Nandi ◽  
S. Chatterjee ◽  
S. K. Samanta ◽  
P. K. Bose ◽  
C. K. Maiti
1991 ◽  
Vol 241 ◽  
Author(s):  
Bijan Tadayon ◽  
Mohammad Fatemi ◽  
Saied Tadayon ◽  
F. Moore ◽  
Harry Dietrich

ABSTRACTWe present here the results of a study on the effect of substrate temperature, Ts, on the electrical and physical characteristics of low temperature (LT) molecular beam epitaxy GaAs layers. Hall measurements have been performed on the asgrown samples and on samples annealed at 610 °C and 850 °C. Si implantation into these layers has also been investigated.


1989 ◽  
Vol 148 ◽  
Author(s):  
Zuzanna Liliental-Weber ◽  
Raymond P. Mariella

ABSTRACTTransmission electron microscopy of GaAs grown on Si for metal-semiconductor-metal photodetectors is presented in this paper. Two kinds of samples are compared: GaAs grown on a 15 Å Si epilayer grown on GaAs, and GaAs grown at low temperature (300°C) on Si substrates. It is shown that the GaAs epitaxial layer grown on thin Si layer has reverse polarity to the substrate (antiphase relation). Higher defect density is observed for GaAs grown on Si substrate. This higher defect density correlates with an increased device speed, but with reduced sensitivity.


1999 ◽  
Vol 28 (3) ◽  
pp. 225-227 ◽  
Author(s):  
Jipo Huang ◽  
Lianwei Wang ◽  
Qinwo Shen ◽  
Chenglu Lin ◽  
Mikael Östling

2018 ◽  
Vol 2018 (1) ◽  
pp. 000728-000733
Author(s):  
Piotr Mackowiak ◽  
Rachid Abdallah ◽  
Martin Wilke ◽  
Jash Patel ◽  
Huma Ashraf ◽  
...  

Abstract In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.


1996 ◽  
Vol 68 (5) ◽  
pp. 699-701 ◽  
Author(s):  
A. K. Verma ◽  
J. Tu ◽  
J. S. Smith ◽  
H. Fujioka ◽  
E. R. Weber

1988 ◽  
Vol 116 ◽  
Author(s):  
S. K. Shastry ◽  
S. Zemon ◽  
C. Armiento ◽  
M. B. Stern ◽  
M. Levinson ◽  
...  

AbstractSignificant progress has been made in the OMVPE growth of GaAs directly on Si by the previously reported low-temperature growth technique. These films have been characterized by low-temperature PL, SIMS, TEM, and DLTS. The epitaxial layers, whose quality has been determined by PL measurements (4.2 K PL spectral width of heavy-hole exciton ≈ 3 meV), were implanted with 29Si+ for fabrication of MESFET channels. Background concentrations of ≈ 1014 cm−3 have been achieved for the first time after rapid thermal annealing without the need to use oxygen implantation or vanadium doping. SIMS measurements do not show Si pileup on the surface or much Si diffusion at the GaAs-Si interface, a significant improvement over earlier results. DLTS measurements and electrical characterization of the GaAs-Si heterojunction diode indicate the presence of only two trap levels (< 1014 cm−3 in concentration) in the GaAs ≥ 2.5 μm away from the interface.


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