Reduction of dislocations in GaAs and InP epitaxial layers by quasi ternary growth and its effect on device performance

1986 ◽  
Vol 15 (4) ◽  
pp. 247-250 ◽  
Author(s):  
H. Beneking ◽  
P. Narozny ◽  
N. Emeis ◽  
K. H. Goetz
Keyword(s):  
Epitaxial Layers ◽  
Device Performance

Measuring Diffusion Lengths in Epitaxial Silicon by Surface Photovoltage

1995 ◽  
Vol 386 ◽  
Author(s):  
John Lowell ◽  
Valerie Wenner ◽  
Damon Debusk
Keyword(s):  
Transition Metals ◽  
Optical Filters ◽  
Surface Photovoltage ◽  
Epitaxial Layers ◽  
Device Performance ◽  
Optical Surface ◽  
Epitaxial Silicon ◽  
Type Silicon ◽  
P Type ◽  
And Diffusion

ABSTRACTIn CMOS, the use of epitaxial layers for prevention of latch-up in logic technologies is well-known and pervasive. One of the crucial parameters is the amount of metallic contamination due to transition metals such as Fe in the epi since this phenomena effects both device performance and quality. However, the ability to measure this parameter on product material is not generally available due to inherent problems with most known methods. The limitation of traditional surface photovoltage is that the deep optical penetration of over a hundred microns is well-beyond the depth of most epitaxial layers and does not accurately profile the epitaxial region [1]. In this paper we report on the application of optical surface photovoltage (SPV) using a set of ultra-shallow optical filters to both quantify and qualify as-grown epitaxial layers on CZ P-type silicon. We believe that a non-contact, SPV measurement of Fe concentration and diffusion lengths within an epitaxial region has not been previously reported.

Uniformity and Morphology of 10 x 100mm 4° Off-Axis 4H-SiC Epitaxial Layers and their Effect on Device Performance

2013 ◽  
Vol 740-742 ◽  
pp. 221-224 ◽  
Author(s):  
Hrishikesh Das ◽  
Swapna Sunkari ◽  
Timothy Oldham ◽  
Josh Rodgers ◽  
Janna Casady
Keyword(s):  
Defect Concentration ◽  
Epitaxial Layers ◽  
Device Performance ◽  
Growth Processes ◽  
Homoepitaxial Layers

Homoepitaxial layers with very good thickness and doping uniformity were grown on 4 inch 4˚ off-axis substrates in a 10x100mm planetary reactor. Process optimizations resulted in reduction of the size of the triangular defects. Aggressive pre-etching of the substrate prior to growth resulted in further suppression of the triangular defect concentration from 3-5cm-2to 0.5cm-2using the same growth processes. Even imperfect areas of the substrate with scratches show suppressed nucleation of triangular defects. JBS diodes with triangular defects show increased leakage depending on the size of the defects. This effect is more pronounced at higher voltages.

Defects in SiC substrates and epitaxial layers affecting semiconductor device performance

2004 ◽  
Vol 27 (1-3) ◽  
pp. 29-35 ◽  
Author(s):  
St. G. Müller ◽  
J. J. Sumakeris ◽  
M. F. Brady ◽  
R. C. Glass ◽  
H. McD. Hobgood ◽  
...  
Keyword(s):  
Semiconductor Device ◽  
Epitaxial Layers ◽  
Device Performance

Processing and Device Performance of GaN Power Rectifiers

1999 ◽  
Vol 595 ◽  
Author(s):  
A.P. Zhang ◽  
G.T. Dang ◽  
X.A. Cao ◽  
H. Cho ◽  
F. Ren ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Breakdown Voltage ◽  
Schottky Contact ◽  
Planar Geometry ◽  
Epitaxial Layers ◽  
Device Performance ◽  
Edge Termination ◽  
Schottky Rectifiers ◽  
Planar Diodes

AbstractMesa and planar geometry GaN Schottky rectifiers were fabricated on 3-12µm thick epitaxial layers. In planar diodes utilizing resistive GaN, a reverse breakdown voltage of 3.1 kV was achieved in structures containing p-guard rings and employing extension of the Schottky contact edge over an oxide layer. In devices without edge termination, the reverse breakdown voltage was 2.3 kV. Mesa diodes fabricated on conducting GaN had breakdown voltages in the range 200-400 V, with on-state resistances as low as 6m Ωcm−2.

scholarly journals Processing And Device Performance Of GaN Power Rectifiers

2000 ◽  
Vol 5 (S1) ◽  
pp. 838-844
Author(s):  
A.P. Zhang ◽  
G.T. Dang ◽  
X.A. Cao ◽  
H. Cho ◽  
F. Ren ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Breakdown Voltage ◽  
Schottky Contact ◽  
Planar Geometry ◽  
Epitaxial Layers ◽  
Device Performance ◽  
Edge Termination ◽  
Schottky Rectifiers ◽  
Planar Diodes

Mesa and planar geometry GaN Schottky rectifiers were fabricated on 3-12µm thick epitaxial layers. In planar diodes utilizing resistive GaN, a reverse breakdown voltage of 3.1 kV was achieved in structures containing p-guard rings and employing extension of the Schottky contact edge over an oxide layer. In devices without edge termination, the reverse breakdown voltage was 2.3 kV. Mesa diodes fabricated on conducting GaN had breakdown voltages in the range 200-400 V, with on-state resistances as low as 6m Ω·cm−2.

Particle characterization of CVD tungsten metallization for 64 MBIT DRAM

1991 ◽  
Vol 49 ◽  
pp. 896-897
Author(s):  
Marylyn Bennett-Lilley ◽  
Thomas T.H. Fu ◽  
David D. Yin ◽  
R. Allen Bowling
Keyword(s):  
Chemical Vapor ◽  
Device Performance ◽  
Particle Characterization ◽  
Particle Generation ◽  
Tungsten Hexafluoride ◽  
Homogeneous Particle ◽  
Multiple Levels ◽  
Circuit Density ◽  
Sources Of Contamination

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

Charging microscopy and cathodoluminescence imaging of semi-insulating gallium arsenide

1986 ◽  
Vol 44 ◽  
pp. 816-817
Author(s):  
T.C. Sheu ◽  
S. Myhajlenko ◽  
D. Davito ◽  
J.L. Edwards ◽  
R. Roedel ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Secondary Electron ◽  
Crystal Defects ◽  
Device Performance ◽  
Gaas Wafer ◽  
Surface Charging ◽  
Gaas Substrates ◽  
Voltage Contrast ◽  
Cathodoluminescence Imaging ◽  
Scanning Electron

Liquid encapsulated Czochralski (LEC) semi-insulating (SI) GaAs has applications in integrated optics and integrated circuits. Yield and device performance is dependent on the homogeniety of the wafers. Therefore, it is important to characterise the uniformity of the GaAs substrates. In this respect, cathodoluminescence (CL) has been used to detect the presence of crystal defects and growth striations. However, when SI GaAs is examined in a scanning electron microscope (SEM), there will be a tendency for the surface to charge up. The surface charging affects the backscattered and secondary electron (SE) yield. Local variations in the surface charge will give rise to contrast (effectively voltage contrast) in the SE image. This may be associated with non-uniformities in the spatial distribution of resistivity. Wakefield et al have made use of “charging microscopy” to reveal resistivity variations across a SI GaAs wafer. In this work we report on CL imaging, the conditions used to obtain “charged” SE images and some aspects of the contrast behaviour.

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