Efficient board interconnect testing using the split boundary scan register

Nazar S. Haider; Nick Kanopoulos

doi:10.1007/bf00971646

Efficient board interconnect testing using the split boundary scan register

Journal of Electronic Testing ◽

10.1007/bf00971646 ◽

1993 ◽

Vol 4 (2) ◽

pp. 181-189

Author(s):

Nazar S. Haider ◽

Nick Kanopoulos

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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BIST and interconnect testing with boundary scan

IEEE Proceedings of the SOUTHEASTCON '91 ◽

10.1109/secon.1991.147692 ◽

2002 ◽

Cited By ~ 4

Author(s):

A.A. Setty ◽

H.L. Martin

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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Implementation of boundary-scan architecture and its application to module interconnect testing

10.14711/thesis-b603889 ◽

1998 ◽

Author(s):

Chun Keung Lo

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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Automated boundary-scan diagnostics: adding value to interconnect testing

Conference Record AUTOTESTCON '92: The IEEE Systems Readiness Technology Conference ◽

10.1109/autest.1992.270090 ◽

2003 ◽

Cited By ~ 2

Author(s):

J.D. Milgram

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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The driver/receiver conflict problem in interconnect testing with boundary-scan

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) ATS-93 ◽

10.1109/ats.1993.398806 ◽

2002 ◽

Cited By ~ 1

Author(s):

L. Jin

Keyword(s):

Boundary Scan ◽

Interconnect Testing ◽

Conflict Problem

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Test Generation: A Boundary Scan Implementation for Module Interconnect Testing

1991, Proceedings. International Test Conference ◽

10.1109/test.1991.519498 ◽

2005 ◽

Cited By ~ 5

Author(s):

M.F. Lefebvre

Keyword(s):

Test Generation ◽

Boundary Scan ◽

Interconnect Testing

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A WORKSTATION ENVIRONMENT FOR BOUNDARY SCAN INTERCONNECT TESTING

1991, Proceedings. International Test Conference ◽

10.1109/test.1991.519779 ◽

2005 ◽

Cited By ~ 1

Author(s):

T.J. Moore

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Integration ◽

10.1016/j.vlsi.2020.02.006 ◽

2020 ◽

Vol 72 ◽

pp. 171-182

Author(s):

Libao Deng ◽

Ning Sun ◽

Ning Fu

Keyword(s):

Boundary Scan ◽

Interconnect Testing ◽

Testing Design

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Novel control pattern generators for interconnect testing with boundary scan

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) ◽

10.1109/dftvs.1999.802876 ◽

2003 ◽

Cited By ~ 4

Author(s):

W. Feng ◽

F.J. Meyer ◽

F. Lombardi

Keyword(s):

Boundary Scan ◽

Interconnect Testing ◽

Control Pattern ◽

Pattern Generators

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Interconnect testing of boards with partial boundary scan

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114070 ◽

2002 ◽

Cited By ~ 20

Author(s):

G.D. Robinson ◽

J.G. Deshayes

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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At-speed boundary-scan interconnect testing in a board with multiple system clocks

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307546 ◽

1999 ◽

Cited By ~ 7

Author(s):

Jongchul Shin ◽

Hyunjin Kim ◽

Sungho Kang

Keyword(s):

Boundary Scan ◽

Interconnect Testing

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