Frequency subtraction circuit

1986 ◽  
Vol 29 (1) ◽  
pp. 34-36
Author(s):  
V. N. Nefedov ◽  
D. D. Savvin
Keyword(s):  
Subtraction Circuit

Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction Circuits

2017 ◽  
Vol 27 (03) ◽  
pp. 1850048
Author(s):  
H. V. Jayashree ◽  
Sharan Patil ◽  
V. K Agrawal
Keyword(s):  
Quantum Computing ◽  
Performance Optimization ◽  
Optical Computing ◽  
Performance Parameters ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Cmos Design ◽  
Low Power Cmos ◽  
And Performance ◽  
Subtraction Circuit

The world of computing is in transition. As chips become smaller and faster, they dissipate more heat, in turn more energy is consumed. Reversible logic is gaining significance in the context of emerging technologies such as quantum computing. Reversible circuits have one-to-one mapping between the inputs and outputs. Hence, there is no loss of energy. Reversible circuits are of high interest in low-power CMOS design, optical computing, nano technology, and quantum computing. In this work, we present designs of reversible Binary Coded Decimal (BCD) adder and unified reversible BCD addition/subtraction circuit. We propose three design approaches for BCD addition. The proposed designs 1 and 2 are aimed at optimizing Garbage Outputs. The proposed design 3 outperforms in all the performance parameters along with producing zero Garbage Outputs compared to proposed designs 1 and 2. We present [Formula: see text] digit reversible BCD addition/subtraction circuit using proposed design 3 for BCD addition to get the benefit of performance parameter optimization. This design outperforms existing counterparts.

A Novel Method for Solution of the Division Operation on ARM7 Microcontroller

2013 ◽  
Vol 718-720 ◽  
pp. 2418-2421
Author(s):  
Guang Wen Wu ◽  
Xiang Sheng Huang ◽  
Wen Long Hu
Keyword(s):  
Program Design ◽  
Digital Circuit ◽  
C Language ◽  
Novel Method ◽  
Function Code ◽  
Arm7 Processor ◽  
The Given ◽  
Subtraction Circuit ◽  
Division Operation

Before architecture V7, the hardware of ARM microcontroller family does not support division operation. Although it is easy to program on ARM processors with C language which can implement division operation with library functions, the procedure has much trouble and the efficiency is lower when the function code written in C language is called in assembly program. This paper introduces an algorithm for the division operation on ARM7 processor and also gives corresponding subroutines which can be used directly in assembly program design. The algorithm is similar to the operation theory of the digital circuit which uses subtraction circuit to do division operation. The given subroutines can deal with the division operation between two 32-bit unsigned integers and the division between a 64-bit unsigned integer and a 32-bit unsigned integer.

scholarly journals Performance Comparison of Multi Input Capacitor Converter Circuits

2018 ◽  
Vol 8 (5) ◽  
pp. 3471
Author(s):  
Sreejith S ◽  
Karthik Balasubramanian
Keyword(s):  
Output Voltage ◽  
Hardware Implementation ◽  
Renewable Energy Sources ◽  
Performance Comparison ◽  
Switched Capacitor ◽  
Grid Systems ◽  
Switched Capacitor Circuits ◽  
Distributed Generators ◽  
High Regard ◽  
Subtraction Circuit

This paper analyze the operation of a multi input switched capacitor (MIC) converters using a couple of switches, diodes and capacitors for several levels. With two input sources it is possible to obtain 8 output voltage levels. Here, 5 topologies of switched capacitor circuits namely summation, subtraction, inverting, double and half circuits are simulated and their performances are analyzed. Multi Input Converters have a high regard for multiple renewable energy sources used in smart grid systems, especially for distributed generators. The effects on output voltage with variation in load for different frequencies are also analyzed. Hardware implementation of summation and subtraction circuit is carried out and the results are compared with the simulated results

scholarly journals Eight-Bit Semiflash A/D Converter

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-7 ◽  
Author(s):  
D. P. Dimitrov ◽  
T. K. Vasileva
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Experimental Results ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sample And Hold ◽  
Reduced Power Consumption ◽  
Subtraction Circuit

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

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