Low Power Scheduling of DAGs to Minimize Finish Times

2006 ◽  
pp. 353-362 ◽  
Author(s):  
Sanjeev Baskiyar ◽  
Kiran Kumar Palli
Keyword(s):  
Low Power ◽  
Power Scheduling

A FAST SCHEDULING ALGORITHM FOR LOW POWER DESIGN

2005 ◽  
Vol 14 (04) ◽  
pp. 735-755
Author(s):  
ASHOK KUMAR ◽  
MAGDY BAYOUMI
Keyword(s):  
Low Power ◽  
Scheduling Algorithm ◽  
Low Power Design ◽  
Power Reduction ◽  
Data Flow Graph ◽  
Maximal Power ◽  
Linear Programming Method ◽  
Voltage Level ◽  
Power Scheduling ◽  
High Level

In this paper, a fast low power scheduling algorithm is presented for high-level synthesis with multiple voltages. The resources are assumed to operate at different voltages and their power consumption and delay for each voltage level is known in advance. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal available parallelism of power hungry operators in an initial schedule. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in quadratic complexity in the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resource-and-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3%–5% of the linear programming method.

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